Superconducting three-terminal device and logic gates
A three-terminal device that exhibits transistor-like functionality at cryogenic temperatures may be formed from a single layer of superconducting material. A main current-carrying channel of the device may be toggled between superconducting and normal conduction states by applying a control signal to a control terminal of the device. Critical-current suppression and device geometry are used to propagate a normal-conduction hotspot from a gate constriction across and along a portion of the main current-carrying channel. The three-terminal device may be used in various superconducting signal-processing circuitry.
1. A dynamically programmable AND/OR logic gate comprising:
two, three-terminal devices connected in parallel and arranged to be connected between a current bias source and a reference potential, wherein each three-terminal device comprises:
a main current-carrying channel configured to be connected between the current bias source and the reference potential;
a gate channel configured to receive a logic input signal and connected to the main current-carrying channel; and
a low-resistance constriction formed in the gate channel proximal the main channel, wherein the constriction is configured to increase a gate current density,
wherein the main current-carrying channel and the gate channel are configured to both be superconducting when in operation.
2. The logic gate of claim 1 , wherein both three-terminal devices are patterned from a single layer of superconducting material.
3. The logic gate of claim 1 , wherein AND logic functionality is obtained by applying a first bias current from the current bias source and OR functionality is obtained by applying a second bias current from the current bias source.
4. The logic gate of claim 3 , wherein the first bias current is less than the second bias current.
5. The logic gate of claim 2 , wherein the superconducting material comprises NbN, YBaCuO, HgTlBaCaCuO, MgB 2 , BISCCO, Nb, NbTiN, NbCN, Al, AlN, WSi, Ga, In, Sn, Pb, or MoGe.
6. The logic gate of claim 1 , wherein each constriction is located within approximately two diffusion lengths of a far edge of a respective main channel at an intersection with the gate channel, wherein one diffusion length L D is given by the following expression
L D =√{square root over (D e τ r )}
where D e is the diffusion constant for electrons in a superconducting material from which the gate channel is formed and τ r is the recombination time for hot electrons in the superconducting material in a superconducting state.
7. The logic gate of claim 1 , wherein each main channel further comprises a narrowed portion extending for a length along each main channel and an intersection of a respective gate channel with each main channel occurs within the length of the narrowed portion.
8. The logic gate of claim 7 , wherein each intersection is located within a downstream half of the length of each narrowed portion.
9. The logic gate of claim 1 , wherein each constriction is of substantially the same size and each main channel is of substantially the same size.
10. The logic gate of claim 1 , further comprising:
an output terminal connected between the current bias source and the main current carrying channels; and
a resistive load connected in series with the output terminal.
11. The three-terminal device of claim 10 , wherein a resistance of the resistive load is any value up to 200,000 ohms.
12. A method of operating a dynamically programmable AND/OR logic gate, the method comprising:
applying a first bias current to two main current carrying channels of two superconducting, three-terminal devices connected in parallel in the programmable AND/OR logic gate;
placing gate channels of the two superconducting, three-terminal devices in superconducting states;
operating the AND/OR logic gate as an AND gate during application of the first bias current;
applying a second bias current to the two main current carrying channels; and
operating the AND/OR logic gate as an OR gate during application of the second bias current.
13. The method of claim 12 , wherein the first bias current is less than the second bias current.
14. The method of claim 12 , further comprising receiving digital signals at the gate channels of the two superconducting, three-terminal devices and providing an output digital signal from the AND/OR logic gate.
15. The method of claim 14 , wherein the gate channels each comprise a constriction formed in the gate channel proximal a respective main channel, wherein the constriction is configured to increase a gate current density.
16. The method of claim 15 , wherein each constriction is located within approximately two diffusion lengths of a far edge of a respective main channel at an intersection with the gate channel, wherein one diffusion length L D is given by the following expression
L D =√{square root over (D e τ r )}
where D e is the diffusion constant for electrons in a superconducting material from which the gate channel is formed and τ r is the recombination time for hot electrons in the superconducting material in a superconducting state.
17. The method of claim 12 , further comprising removing the first bias current or the second bias current to reset the AND/OR logic gate.
18. The method of claim 12 , wherein the two superconducting, three-terminal devices are patterned from a single layer of superconducting material.
19. A logic inverter comprising:
a first three-terminal device comprising a first main current-carrying channel configured to be connected between a current bias source and a main current-carrying terminal of a second superconducting device;
a first gate channel of the first three-terminal device configured to receive a logic input signal and connected to the first main current-carrying channel;
a constriction formed in the first gate channel proximal to the first main current-carrying channel; and
a logic output terminal connected between the first three-terminal device and the second superconducting device.
20. The logic inverter of claim 19 , wherein the first three-terminal device and the second superconducting device are formed from superconducting material.
21. The logic inverter of claim 19 , wherein the first three-terminal device and the second superconducting device are formed from a single layer of superconducting material.
22. The logic inverter of claim 19 , wherein the second superconducting device is a two-terminal device having a second main current-carrying channel.
23. The logic inverter of claim 22 , wherein a minimum width of the second main current-carrying channel is less than a minimum width of the first main current-carrying channel.