Two-state charge-pump control-loop for MEMS DVC control
The present invention generally relates to a DVC having a charge-pump coupled to a MEMS device. The charge-pump is designed to control the output voltage delivered to the electrodes, such as the pull-in electrode or the pull-off electrode, that move the switching element within the MEMS device between locations spaced far from and disposed closely to the RF electrode.
1. A digital variable capacitor, comprising:
a MEMS device having a first electrode, a second electrode, and a third electrode movable between the first electrode and the second electrode;
a waveform controller coupled to the first electrode and the second electrode; and
a charge pump coupled to the waveform controller, the charge pump comprising:
a first capacitor;
a second capacitor coupled to the first capacitor at a first capacitor node;
a first resistor;
a second resistor coupled to the first resistor at a first resistor node, wherein the first resistor node is coupled to the first capacitor node; and
a comparator, wherein the first capacitor node is coupled to the comparator.
2. The digital variable capacitor of claim 1 , further comprising:
a third capacitor coupled to the second capacitor at a second capacitor node; and
a third resistor coupled to the second resistor at a second resistor node.
3. The digital variable capacitor of claim 2 , wherein the second resistor node is coupled to the second capacitor node.
4. The digital variable capacitor of claim 3 , wherein the second resistor and the third resistor have substantially the same value which is different from the value of the first resistor.
5. The digital variable capacitor of claim 4 , wherein the first capacitor, the second capacitor and the third capacitor each have a capacitance that is larger than parasitic capacitances of the first resistor, the second resistor and the third resistor.
6. The digital variable capacitor of claim 5 , wherein a capacitance ratio, which is measured by a capacitance of the first capacitor divided by the total capacitance of the remaining capacitors, is less than a resistive ratio, which is measured by the inverse of a resistance of the first resistor divided by the total resistance of the remaining resistors.
7. The digital variable capacitor of claim 6 , wherein the capacitance ratio is between about 2 to about 10 times less than the resistive ratio.
8. The digital variable capacitor of claim 1 , wherein the comparator is a first comparator, the digital variable capacitor further comprising:
a third capacitor coupled to the second capacitor at a second capacitor node;
a third resistor coupled to the second resistor at a second resistor node;
a fourth resistor coupled to the third resistor at a third resistor node.
9. The digital variable capacitor of claim 8 , wherein the third resistor node is coupled to the second capacitor node.
10. The digital variable capacitor of claim 9 , further comprising a second comparator, wherein the second resistor node is coupled to the second comparator.
11. The digital variable capacitor of claim 10 , wherein the sum of the values of the second resistor and the third resistor substantially equals the value of the fourth resistor.
12. The digital variable capacitor of claim 11 , wherein the first capacitor, the second capacitor and the third capacitor each have a capacitance that is larger than parasitic capacitances of the first resistor, the second resistor, third resistor and the fourth resistor.
13. The digital variable capacitor of claim 12 , wherein a capacitance ratio, which is measured by a capacitance of the first capacitor divided by the total capacitance of the remaining capacitors, is less than a resistive ratio, which is measured by the inverse of a resistance of the first resistor divided by the total resistance of the remaining resistors.
14. The digital variable capacitor of claim 13 , wherein the capacitance ratio is between about 2 to about 10 times less than the resistive ratio.
15. The digital variable capacitor of claim 14 , further comprising a delay circuit coupled to the first comparator.
16. The digital variable capacitor of claim 1 , further comprising:
a first delay circuit coupled to the comparator;
a latch coupled to the comparator; and
a second delay circuit coupled to the latch.
17. The digital variable capacitor of claim 16 , wherein the second delay circuit comprises either an analog delay circuit or a clocked delay-line.
18. The digital variable capacitor of claim 17 , wherein the charge pump further comprises a stabilizing capacitor.
19. The digital variable capacitor of claim 1 , wherein the charge pump further comprises a stabilizing capacitor.
20. The digital variable capacitor of claim 1 , further comprising a delay circuit coupled to the comparator.