Double sampling state retention flip-flop
Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
1. A flip-flop circuit, the flip-flop circuit comprising:
a master latch;
a slave latch connected to the master latch;
a dual-function circuit connected to the master latch and the slave latch and configured to perform state retention and double sampling;
a control circuit configured to generate a plurality of control signals for the flip-flop circuit based on a clock signal and a delayed version of the clock signal; and
an error logic circuit configured to generate an error signal based on signals from the master latch, the dual-function circuit, and the control circuit.
2. The flip-flop circuit of claim 1 , wherein the dual-function circuit comprises:
a balloon latch connected to the slave latch and configured to perform state retention; and
a shadow latch connected to the master latch and configured to perform double sampling.
3. The flip-flop circuit of claim 2 , further comprising a plurality of switch circuits connected to an input terminal of the flip-flop circuit, to the master latch, to the slave latch, to the balloon latch, and to the shadow latch.
4. The flip-flop circuit of claim 2 , wherein the balloon latch comprises a first pair of inverters and a first switch configured to be controlled by a first pair of complementary signals.
5. The flip-flop circuit of claim 4 , wherein the shadow latch comprises a second pair of inverters and a second switch configured to be controlled by a second pair of complementary signals.
6. The flip-flop circuit of claim 1 , wherein the dual-function circuit comprises a shared latch configured to perform state retention and double sampling in response to a first pair of complementary signals.
7. The flip-flop circuit of claim 6 , wherein the shared latch comprises a pair of inverters and a switch configured to be controlled by the first pair of complementary signals.
8. The flip-flop circuit of claim 6 , further comprising a plurality of switch circuits connected to an input terminal of the flip-flop circuit, to the master latch, to the slave latch, and to the shared latch.
9. The flip-flop circuit of claim 8 , further comprising:
a multiplexer logic circuit configured to generate a plurality of complementary signals for transmission gates of the shared latch and the switch circuits.
10. A flip-flop device comprising the flip-flop circuit of claim 1 , a power management unit configured to generate a power-on signal and a power-off signal for the flip-flop circuit, and a clock generation unit configured to generate clock signals for the flip-flop circuit.
11. A flip-flop circuit, the flip-flop circuit comprising:
a master latch;
a slave latch connected to the master latch;
a dual-function circuit connected to the master latch and the slave latch and configured to perform state retention and double sampling;
a plurality of switch circuits connected to an input terminal of the flip-flop circuit, to the master latch, to the slave latch, and to the dual-function circuit;
a control circuit configured to generate a plurality of control signals for the switch circuits based on a clock signal and a delayed version of the clock signal; and
an error logic circuit configured to generate an error signal based on signals from the master latch, the dual-function circuit, and the control circuit.
12. The flip-flop circuit of claim 11 , wherein the dual-function circuit comprises:
a balloon latch connected to the slave latch and configured to perform state retention, wherein the balloon latch comprises a first pair of inverters and a first switch configured to be controlled by a first pair of complementary signals; and
a shadow latch connected to the master latch and configured to perform double sampling, wherein the shadow latch comprises a second pair of inverters and a second switch configured to be controlled by a second pair of complementary signals.
13. The flip-flop circuit of claim 11 , wherein the master latch and the slave latch comprise a plurality of transmission gates configured to be controlled by the clock signal and a complementary clock signal of the clock signal.
14. The flip-flop circuit of claim 11 , further comprising:
a multiplexer logic circuit configured to generate a plurality of complementary signals for transmission gates of the dual-function circuit and the switch circuits.
15. The flip-flop circuit of claim 14 , wherein the dual-function circuit comprises a shared latch configured to perform state retention and double sampling in response to a first pair of complementary signals from the multiplexer logic circuit, and wherein the shared latch comprises a pair of inverters and a switch configured to be controlled by the first pair of complementary signals.
16. A method for operating a flip-flop circuit, the method comprising:
performing double-sampling using a dual-function circuit of the flip-flop circuit;
performing state retention using the dual-function circuit of the flip-flop circuit;
generating a plurality of control signals for the flip-flop circuit based on a clock signal and a delayed version of the clock signal using a control circuit of the flip-flop circuit; and
generating an error signal based on signals from a master latch of the flip-flop circuit, the dual-function circuit, and the control circuit.