IP Library Granted Patent US 9,678,790
Granted Patent B2
US 9,678,790 · App. 14/792,740 · Granted Jun 13, 2017

Devices and methods implementing operations for selective enforcement of task dependencies

Inventors: Arun Raman (Fremont, CA); Pablo Montesinos Ortego (Fremont, CA)
Assignee: QUALCOMM Incorporated
G06F9/4843G06F9/4881
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Quick Facts
Patent No.
US 9,678,790
App. No.
14/792,740
Granted
Jun 13, 2017
Kind
B2
Abstract

A method and computing device, for enabling selective enforcement of complex task dependencies. The method and allows a computing device to determine whether to enforce task-dependencies based on programmer or end-user goals concerning efficiency and quality of runtime experience. A computing device may be configured to schedule executing a first task, identify an operation (e.g., a “+>” operation) of the first task as being selectively dependent on a second task finishing execution, and determining whether to enforce the dependency of the first task on the second task based on an evaluation of one or more enforcement conditions. If the enforcement conditions are not met, enforcing the dependency, executing the second task, and withholding execution of the first task until execution of the second task has finished. If the enforcement conditions are met, commencing execution of the first task prior to, or parallel to the second task finishing execution.

Claims (59)

1. A method of executing tasks in a computing device, comprising implementing a first operator for selective enforcement of intertask execution dependencies, comprising:

commencing execution of a first task via a first thread of a thread pool in the computing device;

identifying whether there exists a second task ready for execution such that an operation of the second task identifies the second task as either being dependent on the first task finishing execution or being selectively dependent on the first task finishing execution;

identifying whether there exists a third task ready for execution such that an operation of the second task identifies the second task as either being dependent on the third task finishing execution or being selectively dependent on the third task finishing execution;

commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being dependent on the third task finishing execution;

determining whether to enforce the selective dependency of the second task on the third task by determining whether one or more enforcement conditions are satisfied in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the third task finishing execution;

ignoring the selective dependency, and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are met; and

commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to determining that the one or more enforcement conditions are not met, enforcing the selective dependency.

2. The method of claim 1 , further comprising implementing a second operation for mandatory enforcement of intertask execution dependencies.

3. A computing device, comprising:

a processor configured with processor-executable instructions to perform operations comprising implementing a first operation for selective enforcement of intertask execution dependencies comprising:

commencing execution of a first task via a first thread of a thread pool in the computing device;

identifying whether there exists a second task ready for execution such that an operation of the second task identifies the second task as either being dependent on the first task finishing execution or being selectively dependent on the first task finishing execution;

identifying whether there exists a third task ready for execution such that an operation of the second task identifies the second task as either being dependent on the third task finishing execution or being selectively dependent on the third task finishing execution;

commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being dependent on the third task finishing execution;

determining whether to enforce the selective dependency of the second task on the third task by determining whether one or more enforcement conditions are satisfied in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the third task finishing execution;

ignoring the selective dependency, and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are met; and

commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to determining that the one or more enforcement conditions are not met, enforcing the selective dependency.

4. The computing device of claim 3 , wherein the processor is configured with processor-executable instructions to perform operations further comprising implementing a second operation for mandatory enforcement of intertask execution dependencies.

5. The computing device of claim 3 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies comprises:

identifying whether any additional operations of the second task are either dependent or selectively dependent on any additional tasks other than the first task and third tasks finishing execution.

6. The computing device of claim 3 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies comprises:

commencing execution of the second task via a second thread of the thread pool only after determining that additional tasks have finished execution in response to identifying that there exist additional tasks ready for execution such that an operation of the second task identifies the second task as being dependent on the additional tasks finishing execution.

7. The computing device of claim 6 , wherein the processor is configured with processor-executable instructions to perform operations such that implementing a first operation for selective enforcement of intertask execution dependencies further comprises:

in response to identifying that there exist additional tasks ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the additional tasks finishing execution:

determining whether to enforce the selective dependency of the second task on the additional tasks by determining whether the one or more enforcement conditions are satisfied;

ignoring the selective dependency and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are not met; and

enforcing the dependency and commencing execution of the second task via a second thread of the thread pool only after determining that the additional tasks have finished execution in response to determining that the one or more enforcement conditions are met.

8. The computing device of claim 3 , wherein the processor is configured with processor-executable instructions to perform operations such that:

commencing execution of the first task via the first thread of the thread pool comprises executing the first task in a first processing core of the computing device; and

commencing execution of the second task via the second thread of the thread pool comprises executing the second task in a second processing core of the computing device prior to or concurrent with execution of the first task in the first processing core.

9. The computing device of claim 3 , wherein the processor is configured with processor-executable instructions to perform operations such that the one or more enforcement conditions are evaluated at the time of execution.

10. The computing device of claim 3 , wherein the processor is further configured with processor-executable instructions to perform operations comprising:

receiving execution preference information prior to commencing execution of the first task; and

setting the one or more enforcement conditions in response to receiving the execution preference information and based upon the execution preference information.

11. A non-transitory processor-readable storage medium having stored thereon processor-executable instructions to cause a processor to perform operations comprising implementing a first operation for selective enforcement of intertask execution dependencies comprising:

commencing execution of a first task via a first thread of a thread pool in the computing device;

identifying whether there exists a second task ready for execution such that an operation of the second task identifies the second task as either being dependent on the first task finishing execution or being selectively dependent on the first task finishing execution;

identifying whether there exists a third task ready for execution such that an operation of the second task identifies the second task as either being dependent on the third task finishing execution or being selectively dependent on the third task finishing execution;

commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being dependent on the third task finishing execution;

determining whether to enforce the selective dependency of the second task on the third task by determining whether one or more enforcement conditions are satisfied in response to identifying that there exists a third task ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the third task finishing execution;

ignoring the selective dependency, and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are met; and

commencing execution of the second task via a second thread of the thread pool only after determining that the third task has finished execution in response to determining that the one or more enforcement conditions are not met, enforcing the selective dependency.

12. The non-transitory processor-readable storage medium of claim 11 , wherein the processor-executable instructions are configured to cause a processor to perform operations further comprising implementing a second operation for mandatory enforcement of intertask execution dependencies.

13. The non-transitory processor-readable storage medium of claim 11 , wherein the processor-executable instructions are configured to cause a processor of a computing device to perform operations such that that implementing a first operation for selective enforcement of intertask execution dependencies comprises:

identifying whether any additional operations of the second task are either dependent or selectively dependent on any additional tasks other than the first task and third tasks finishing execution.

14. The non-transitory processor-readable storage medium of claim 13 , wherein the processor-executable instructions are configured to cause a processor of a computing device to perform operations such that that implementing a first operation for selective enforcement of intertask execution dependencies comprises:

commencing execution of the second task via a second thread of the thread pool only after determining that the additional tasks have finished execution in response to identifying that there exist additional tasks ready for execution such that an operation of the second task identifies the second task as being dependent on the additional tasks finishing execution.

15. The non-transitory processor-readable storage medium of claim 13 , wherein the processor-executable instructions are configured to cause a processor of a computing device to perform operations such that that implementing a first operation for selective enforcement of intertask execution dependencies comprises further comprises:

in response to identifying that there exist additional tasks ready for execution such that an operation of the second task identifies the second task as being selectively dependent on the additional tasks finishing execution:

determining whether to enforce the selective dependency of the second task on the additional tasks by determining whether the one or more enforcement conditions are satisfied;

ignoring the selective dependency and commencing execution of the second task via a second thread of the thread pool in response to determining that the one or more enforcement conditions are not met; and

enforcing the dependency and commencing execution of the second task via a second thread of the thread pool only after determining that the additional tasks have finished execution in response to determining that the one or more enforcement conditions are met.

16. The non-transitory processor-readable storage medium of claim 11 , wherein the processor-executable instructions are configured to cause a processor of a computing device to perform operations such that:

commencing execution of the first task via the first thread of the thread pool comprises executing the first task in a first processing core of the computing device; and

commencing execution of the second task via the second thread of the thread pool comprises executing the second task in a second processing core of the computing device prior to or concurrent with execution of the first task in the first processing core.

17. The non-transitory processor-readable storage medium of claim 11 , wherein the processor-executable instructions are configured to cause a processor of a computing device to perform operations further comprising:

receiving execution preference information prior to commencing execution of the first task; and

setting the one or more enforcement conditions in response to the receiving and based upon the execution preference information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2015
From: RAMAN, ARUN; MONTESINOS ORTEGO, PABLO
To: QUALCOMM INCORPORATED
Reel/Frame 036544/0327 →
Continuity (2)
Provisional Application 62100690 · Jan 7, 2015
Related Publication 20160196162A1 · Jul 7, 2016