IP Library Granted Patent US 9,264,102
Granted Patent B2
US 9,264,102 · App. 14/793,582 · Granted Feb 16, 2016

Trace canceller with equalizer adjusted for trace length driving variable-gain amplifier with automatic gain control loop

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Quick Facts
Patent No.
US 9,264,102
App. No.
14/793,582
Granted
Feb 16, 2016
Kind
B2
Abstract

Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Claims (30)

1. A circuit, comprising:

an equalizer configured to receive an input signal and to compensate for distortion of the input signal thereby generating an equalized signal;

an amplifier configured to receive the equalized signal from the equalizer and to amplify the equalized signal in response to a control signal thereby generating an amplified signal;

a buffer configured to receive the amplified signal from the amplifier and to generate an output signal in response to the amplified signal; and

a control circuit configured to receive the input signal and the output signal and to generate the control signal in response to the input signal and the output signal such that operation of the buffer remains in a linear region.

2. The circuit of claim 1 , wherein the equalizer is configured to compensate for the distortion of the input signal in response to a second control signal that represents a characteristic of a transmission line by which the input signal is received.

3. The circuit of claim 2 , wherein the characteristic of the transmission line is a length of the transmission line.

4. The circuit of claim 1 , wherein the equalizer is configured to compensate for both amplitude distortion and phase distortion of the input signal.

5. The circuit of claim 1 , wherein the equalizer is configured to adjustably control attenuation of different frequency components of the input signal.

6. The circuit of claim 1 , wherein the equalizer includes active components, passive components, or a combination of active and passive components.

7. The circuit of claim 1 , wherein the control circuit is configured to generate the control signal such that a low frequency swing of the output signal is about the same as a low frequency swing of the input signal.

8. The circuit of claim 1 , wherein the control circuit is configured to generate the control signal by comparing a low frequency swing of the input signal to a low frequency swing of the output signal.

9. The circuit of claim 1 , wherein either or both of the amplifier and the buffer are linear circuits.

10. The circuit of claim 1 , wherein the equalizer, amplifier, buffer, and control circuit are all either differential circuits or single-ended circuits.

11. A transmission line assembly, comprising:

a first transmission line configured to transmit a first signal;

an equalizer configured to receive the first signal from the first transmission line and to compensate for distortion of the first signal resulting from transmission of the first signal by the first transmission line thereby generating an equalized signal;

an amplifier configured to receive the equalized signal from the equalizer and to amplify the equalized signal in response to a control signal thereby generating an amplified signal;

a buffer configured to receive the amplified signal from the amplifier and to generate a second signal in response to the amplified signal;

a second transmission line configured to transmit the second signal; and

a control circuit configured to receive the first signal and the second signal and to generate the control signal in response to the first signal and the second signal such that operation of the buffer remains in a linear region.

12. The transmission line assembly of claim 11 , wherein the equalizer is configured to compensate for the distortion of the first signal in response to a second control signal that represents a characteristic of the first transmission line.

13. The transmission line assembly of claim 12 , wherein the characteristic of the first transmission line is a length of the first transmission line.

14. The transmission line assembly of claim 11 , wherein the equalizer is configured to compensate for both amplitude distortion and phase distortion of the first signal.

15. The transmission line assembly of claim 11 , wherein the equalizer is configured to adjustably control attenuation of different frequency components of the first signal.

16. The transmission line assembly of claim 11 , wherein the equalizer includes active components, passive components, or a combination of active and passive components.

17. The transmission line assembly of claim 11 , wherein the control circuit is configured to generate the control signal such that a low frequency swing of the second signal is about the same as a low frequency swing of the first signal.

18. The transmission line assembly of claim 11 , wherein the control circuit is configured to generate the control signal by comparing a low frequency swing of the first signal to a low frequency swing of the second signal.

19. The transmission line assembly of claim 11 , wherein either or both of the amplifier and the buffer are linear circuits.

20. The transmission line assembly of claim 11 , wherein the equalizer, amplifier, buffer, and control circuit are all either differential circuits or single-ended circuits.

Assignments (3)
SECURITY AGREEMENT Recorded Jan 23, 2018
From: DIODES INCORPORATED
To: BANK OF AMERICA, N.A., AS ADMIN. AGENT
Reel/Frame 045195/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2017
From: PERICOM SEMICONDUCTOR CORPORATION
To: DIODES INCORPORATED
Reel/Frame 044975/0554 →
SECURITY INTEREST Recorded Oct 27, 2016
From: PERICOM SEMICONDUCTOR CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 040154/0360 →