Timing controller and display device including the same

1. A timing controller comprising:

a receiver receiving a still image signal indicating that an image to be displayed is a still image;

a transmitter outputting an output data used to display images;

a clock frequency generator generating a spread clock signal having a frequency value adjusted between first and second frequency values by modulating a reference clock signal;

a memory system including a memory device, the memory device storing a first image data which corresponds to a first frame of an image displayed and is received through the receiver in response to the spread clock signal, and the memory system outputting the first image data in response to the spread clock signal; and

a still image manager communicating with the memory system to output the first image data as the output data in response to the still image signal.

2. The timing controller of claim 1 , wherein the spread clock signal has the first and second frequency values for each modulation period according to a control of the clock frequency generator.

3. The timing controller of claim 2 , wherein the first and second frequency values and the modulation period are modified based on an operating environment of the memory system.

4. The timing controller of claim 1 , wherein the receiver is configured to operate according to eDP interface protocol.

5. The timing controller of claim 1 , wherein the memory system is implemented as an embedded DRAM.

6. A timing controller configured to operate a display device, the timing controller comprising:

a receiver configured to receive a first image data corresponding to a first frame of an image displayed on a display panel of the display device, and receive at least one of either a second image data or a still image signal, wherein the second image data corresponds to a second frame following a first frame, and the still image signal indicates that an image displayed on a display panel of a display device is a still image;

a memory system configured to store the first image data;

a data processor configured to process the second image data when the still image signal is not provided;

a still image manager, in response to the still image signal, configured to communicate with the memory system to output the first image data from the memory system; and

a transmitter configured to output one of either a first image data output from the memory system or the second image data processed by the data processing unit,

wherein the memory system includes:

a clock frequency generator configured to generate a spread clock signal having a frequency value adjusted between first and second frequency values;

a memory device configured to store the first image data in response to the spread clock signal; and

a memory controller configured to control storage and output of the first image data in response to the spread clock signal.

7. The timing controller of claim 6 , wherein the memory system further includes a modulation controller configured to modify a period by which the first frequency value, second frequency values, and the frequency value of the spread clock signal are adjusted based on an operating environment of the memory system.

8. The timing controller of claim 6 , wherein the receiver is configured to receive one of either a still image signal or continuous image signal indicating that an image displayed as the second frame is not a still image.

9. The timing controller of claim 8 , wherein the data processor is configured to process the second image date in response to the continuous image signal.

10. The timing controller of claim 6 , wherein when the still image signal is not provided, the memory device of the memory system is further configured to store the second image data, and

the receiver is further configured to receive at least one of either a third image data or an additional still image signal,

wherein the third image data corresponds to a third frame following the second frame, and the additional still image signal indicates that an image displayed as the third frame is a still image.

11. The timing controller of claim 10 , wherein when the additional still image signal is not provided, the data processor is further configured to process the third image data.

12. The timing controller of claim 10 , wherein the still image manager is further configured to communicate with the memory system in response to the additional still image signal in order to output the second image data from the memory system.

13. The timing controller of claim 12 , wherein the memory controller is further configured to control the storage and the output of the second image data in response to the spread clock signal.

14. A display device comprising:

a display panel;

a gate driver;

a data driver;

a timing controller which is configured to:

receive, from a host, a first image data corresponding to a first frame and a still image signal indicating that an image displayed as a second frame following the first frame is a still image,

output an output data used to generate the data voltages, and

control the gate driver and the data driver;

a clock frequency generator configured to generate a spread clock signal having a frequency value adjusted between first and second frequency values by modulating a reference clock signal; and

a memory system including a memory device, the memory device configured to store the first image data in response to the spread clock signal and output the first image data in response to the spread clock signal,

wherein the timing controller is further configured to communicate with the memory system to output the first image data output from the memory system as an output data in response to the still image signal.

15. The display device of claim 14 , wherein the clock frequency generator is configured to modulate the reference clock signal through a spread spectrum clock generation (SSCG) method.

16. The display device of claim 14 , wherein the reference clock signal is provided from the host, or is generated inside the timing controller.

17. The display device of claim 14 , wherein when the still image signal is not provided from the host, the timing controller is further configured to receive the second image data from the host, process the second image data, and output the processed second image data as the output data.

18. The display device of claim 14 , wherein the memory system is implemented as an SDRAM.