Discrete Three-Dimensional Vertical Memory
The present invention discloses a discrete three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component for the 3D-M V arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.
1 . A discrete three-dimensional vertical memory (3D-M V ), comprising:
a 3D-array die comprising at least a 3D-M V array, wherein said 3D-M V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M V array;
wherein said off-die peripheral-circuit component is absent from said 3D-array die; the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said peripheral-circuit die; and, said 3D-array die and said peripheral-circuit die are separate dice.
2 . The memory according to claim 1 , wherein said off-die peripheral-circuit component is selected from a group of peripheral-circuit components consisting of read-voltage generator, write-voltage generator, address translator and data translator.
3 . The memory according to claim 1 , wherein said 3D-array die further comprises at least an in-die peripheral-circuit component of said 3D-M V array, and the number of interconnect levels of said off-die peripheral-circuit component is more than the number of interconnect levels of said in-die peripheral-circuit component.
4 . The memory according to claim 1 , wherein said 3D-array die further comprises at least an in-die peripheral-circuit component of said 3D-M V array, and said off-die peripheral-circuit component and said in-die peripheral-circuit component comprise different interconnect materials.
5 . The memory according to claim 1 , wherein said 3D-M V is a vertical-NAND.
6 . The memory according to claim 1 , wherein each of said memory cells comprises at least a vertical transistor.
7 . The memory according to claim 1 , wherein said 3D-M V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
8 . The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.
9 . The memory according to claim 1 , further comprising another 3D-array die including at least another 3D-M V array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.
10 . A discrete three-dimensional vertical memory (3D-M V ), comprising:
a 3D-array die comprising at least a 3D-M V array and an in-die peripheral-circuit component of said 3D-M V array, wherein said 3D-M V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M V array;
wherein said off-die peripheral-circuit component is absent from said 3D-array die; said off-die peripheral-circuit component and said in-die peripheral-circuit component comprise different interconnect materials; and, said 3D-array die and said peripheral-circuit die are separate dice.
11 . The memory according to claim 10 , wherein said off-die peripheral-circuit component is selected from a group of peripheral-circuit components consisting of read-voltage generator, write-voltage generator, address translator and data translator.
12 . The memory according to claim 10 , wherein said in-die peripheral-circuit component comprises high-temperature interconnect materials.
13 . The memory according to claim 10 , wherein said off-die peripheral-circuit component comprises high-speed interconnect materials.
14 . The memory according to claim 10 , wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said peripheral-circuit die.
15 . The memory according to claim 10 , wherein the number of interconnect levels of said off-die peripheral-circuit component is more than the number of interconnect levels of said in-die peripheral-circuit component.
16 . The memory according to claim 10 , wherein said 3D-M V is a vertical-NAND.
17 . The memory according to claim 10 , wherein each of said memory cells comprises at least a vertical transistor.
18 . The memory according to claim 10 , wherein said 3D-M V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
19 . The memory according to claim 10 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.
20 . The memory according to claim 10 , further comprising another 3D-array die including at least another 3D-M V array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.