IP Library Granted Patent US 9,437,716
Granted Patent B2
US 9,437,716 · App. 14/803,751 · Granted Sep 6, 2016

Semiconductor device comprising a graphene wire

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Quick Facts
Patent No.
US 9,437,716
App. No.
14/803,751
Granted
Sep 6, 2016
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

Claims (21)

1. A semiconductor device comprising:

a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction and having a convex cross-sectional surface in a plane perpendicular to the first longitudinal direction; and

a graphene layer provided on the metal layer to surround a side surface and an upper surface of a convex portion of the metal layer, the graphene layer having a curved cross-sectional surface and extending in the first longitudinal direction,

wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and

wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface ( 111 ) alignment.

2. The semiconductor device of claim 1 , wherein the first portion is an underlying layer, and the second portion is a catalyst layer.

3. The semiconductor device of claim 1 , wherein an end portion of the graphene layer contacts at least one of an upper surface of the first portion and a side surface of the second portion.

4. The semiconductor device of claim 1 , wherein a facet is provided on a side surface of the second portion, and an end portion of the graphene layer contacts the facet.

5. The semiconductor device of claim 1 , wherein the upper surface of the second portion is narrower than the lower surface of the second portion.

6. The semiconductor device of claim 1 , wherein the graphene layer is formed in a roll shape.

7. The semiconductor device of claim 6 , wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and a width of the first portion is set according to a required roll diameter of the graphene layer.

8. A semiconductor device comprising:

a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction; and

a graphene layer provided on the metal layer to surround a side surface and an upper surface of the metal layer, the graphene layer extending in the first longitudinal direction and having a convex cross-sectional surface with respect to the metal layer in a plane perpendicular to the first longitudinal direction,

wherein the metal layer comprises a first portion having a first width and including the upper surface, and a second portion which is provided on the first portion and which has a second width smaller than the first width, the second portion having a tapered shape whose widths of upper and lower surfaces are different, and has surface ( 111 ) alignment, and

wherein the graphene layer comprises a plurality of graphene sheets which are stacked, and a portion of end portions of the graphene sheets is in contact with the upper surface of the first portion of the metal layer.

9. The semiconductor device of claim 8 , wherein the first portion is an underlying layer, and the second portion is a catalyst layer.

10. The semiconductor device of claim 8 , wherein a facet is provided on a side surface of the second portion, and another portion of end portions of the graphene sheets is in contact with the facet.

11. The semiconductor device of claim 8 , wherein the upper surface of the second portion is narrower than the lower surface of the second portion.

12. The semiconductor device of claim 8 , wherein the graphene layer is formed in a roll shape.

13. The semiconductor device of claim 12 , wherein the width of the first portion is set according to a required roll diameter of the graphene layer.

Assignments (4)
DE-MERGER Recorded Dec 12, 2019
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051260/0291 →
MERGER Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION; K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051262/0776 →
CHANGE OF NAME AND ADDRESS Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 051262/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2015
From: WADA, MAKOTO; YAMAZAKI, YUICHI; KAJITA, AKIHIRO; ISOBAYASHI, ATSUNOBU; SAITO, TATSURO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036136/0406 →