Data encoding using spare channels
Implementations of encoding techniques are disclosed. In one embodiment, an encoding system includes a codec device, a switching network, a rerouting circuit, a logic integrated circuit, and memory devices. The codec device includes a plurality of input and output (I/O) ports to transport data signals. The switching network is coupled both to the plurality of I/O ports and to a plurality of channels external to the device. The plurality of I/O ports includes at least one spare channel. The rerouting circuitry is coupled to and configured to control the switching network and the logic integrated circuit has logic circuity including command and decode queueing circuitry, redundancy circuits, and error correction circuitry. The memory devices do include any circuitry included in the logic circuitry. Other systems and apparatuses are also described.
1. An apparatus, comprising:
a codec device having a first plurality of input and output (I/O) ports and a second plurality of I/O ports, the first plurality of I/O ports and the second plurality of I/O ports each configured to transport data signals, the second plurality of I/O ports including at least one encoding indicator I/O port to transport an encoding indicator signal; and
a switching network coupled to the second plurality of I/O ports and coupleable to a plurality of channels external to the device, the plurality of channels including a plurality of data channels and at least one spare channel to transport at least one signal type selectable from either a data signal rerouted from a faulty one of the plurality of channels exterior to the device and an encoding indicator signal.
2. The apparatus of claim 1 , further comprising rerouting circuitry coupled to and configured to control the switching network.
3. The apparatus of claim 2 , wherein the rerouting circuitry comprises a slave controller configured to operate under control of one or more corresponding master controllers.
4. The apparatus of claim 2 , wherein the rerouting circuitry is configured query the status of the at least one spare channel prior to using selected ones of the at least spare channel to transport the encoding indicator signal.
5. The apparatus of claim 1 , further comprising data bus inversion (DBI) control circuitry to enable the codec device and to signal the switching network to route the encoding indicator signal to the spare channel.
6. The apparatus of claim 1 , wherein the codec device is a data bus inversion (DBI) codec.
7. The apparatus of claim 1 , further comprising a plurality of memory integrated circuits.
8. The apparatus of claim 1 , further comprising a logic integrated circuit having logic circuity, the logic circuitry including command and decode queueing circuitry and redundancy circuits.
9. The apparatus of claim 8 , further comprising a plurality of memory integrated circuits, each of the plurality of memory integrated circuits being configured not to include any circuitry included in the logic circuitry of the logic integrated circuit.
10. The integrated circuit of claim 1 , wherein the switching network is further configured reroute an original data signal destined from the faulty one of the plurality of channels to a selected one of the at least one spare channel.
11. A system, comprising:
a codec device having a plurality of input and output (I/O) ports configured to transport data signals;
a switching network coupled to the plurality of I/O ports and coupleable to a plurality of channels external to the device, the plurality of I/O ports including at least one spare channel, the at least one spare channel to transport at least one signal type selectable from either a data signal rerouted from a faulty one of the plurality of channels exterior to the device and an encoding indicator signal;
rerouting circuitry coupled to and configured to control the switching network;
a logic integrated circuit having logic circuity, the logic circuitry including command and decode queueing circuitry, redundancy circuits, and error correction circuitry; and
a plurality of memory integrated circuit devices not including any circuitry included in the logic circuitry.
12. The system of claim 11 , wherein the plurality of I/O ports include at least one encoding indicator I/O port to transport an encoding indicator signal.
13. The system of claim 11 , wherein the plurality of memory integrated circuit devices is a peripheral device, separate from the logic integrated circuit.
14. The system of claim 11 , further comprising a memory controller external to the system, the plurality of memory integrated circuit devices and the logic integrated circuit being arranged as a vertically-stacked memory module and coupled to the external memory controller.
15. The system of claim 11 , wherein the switching network is to transport a data signal rerouted from a faulty one of the plurality of I/O ports to a selected one of the at least one spare channel.
16. The system of claim 11 , wherein the switching network is to transport one signal type selected from a data signal and an encoding indicator signal to the at least one spare channel.
17. The system of claim 16 , wherein the rerouting circuitry is configured to query the status of the at least one spare channel prior to using a selected one of the at least spare channel to transport the encoding indicator signal.
18. The system of claim 11 , wherein the plurality of channels comprises through-substrate interconnects.
19. The system of claim 11 , wherein the through-substrate interconnects include at least one through-substrate interconnect dedicated to carrying a data bus inversion signal.
20. A system, comprising:
a codec device to encode a node a plurality of data signals written to or read from a memory array, the codec device to encode and decode based on at least one algorithm and at least one received encoding signal;
a switching network coupled to the codec device and coupleable to a plurality of channels external to the circuit, the plurality of channels including a plurality of data channels and at least one spare channel, the at least one spare channel to transport at least one signal type selectable from either a data signal rerouted from a faulty one of the plurality of channels exterior to the device and an encoding indicator signal;
rerouting circuitry coupled to and configured to control the switching network, the rerouting circuitry to direct the switching network to reroute at least one data signal to a selected on of the at least one spare channel based on a detection of a faulty one of the plurality of data channels.
21. The system of claim 20 , wherein the codec device is a data bus inversion (DBI) codec device, the received encoding signal is a DBI signal, and the at least one algorithm includes at least one DBI algorithm.
22. The system of claim 21 , wherein the DBI codec device is to encode the plurality of data signals onto selected ones of the plurality of channels and generate a corresponding DBI hit on a selected one of the at least one spare channel.
23. The system of claim 21 , wherein, based on a determination that only one spare channel of the at least one spare channel is not being used for rerouting data signals, the at least one DBI algorithm is be performed on each of the data signals, and one DBI signal is to be coupled to a selected one of the at least one spare channel.
24. The system of claim 20 , wherein the system is integrated into a single package.