IP Library › Granted Patent US 9,898,141
Granted Patent B2
US 9,898,141 · App. 14/804,785 · Granted Feb 20, 2018

Touch panel, method for fabricating the same and touch display device

Inventors: Chunwei Wu (Beijing, CN); Chungchun Lee (Beijing, CN); Yanfeng Wang (Beijing, CN); Xiaoguang Xu (Beijing, CN)
Assignee: BOE Technology Group Co., Ltd.
G06F3/042G06F3/0412G06F3/0416H01L27/14678H01L31/028H01L31/0296H01L31/02164H01L31/1136H01L31/1828H01L31/202G06F2203/04103G06F2203/04107
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Quick Facts
Patent No.
US 9,898,141
App. No.
14/804,785
Granted
Feb 20, 2018
Kind
B2
Abstract

A touch panel, a method for fabricating the same and a touch display device are disclosed. The touch panel includes touch units, each of which includes: a capacitor having a first terminal connected to a first bias voltage; a first transistor having an amorphous silicon active layer, one of a source and a drain of the first transistor is connected to a third bias voltage and the other is connected to a second terminal of the capacitor; a second transistor having an oxide semiconductor active layer, a gate of the second transistor is connected to a scan line, one of a source and a drain of the second transistor is connected to the second terminal of the capacitor and the other is connected to a data line. The touch panel further includes a light-shielding layer; an aperture portion is disposed on a part of the light-shielding layer.

Claims (11)

1. A method for fabricating a touch panel, comprising:

forming a gate electrode of a first transistor and a gate electrode of a second transistor on a substrate;

forming a gate insulation layer;

forming an active layer of the first transistor in at least a part of region of the gate insulation layer that corresponds to the gate electrode of the first transistor; and

forming an active layer of the second transistor in at least a part of region of the gate insulation layer that corresponds to the gate electrode of the second transistor;

wherein the active layer of the first transistor is formed from amorphous silicon and the active layer of the second transistor is formed from oxide semiconductor;

wherein before forming the active layer of the first transistor, the method further comprises: forming a protection layer overlaying the active layer of the second transistor and removing the protection layer through an etching process.

2. The method of claim 1 , further comprising:

forming an etch stop layer on the active layer of the second transistor, wherein a via hole is formed in the etch stop layer;

forming a source electrode and a drain electrode of the first transistor as well as a source electrode and a drain electrode of the second transistor; and

forming a passivation layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2015
From: WU, CHUNWEI; LEE, CHUNGCHUN; WANG, YANFENG; XU, XIAOGUANG
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 036183/0300 →
Priority Claims (1)
CN 2015 1 0145776 · Mar 30, 2015 · national
Continuity (1)
Related Publication 20160291714A1 · Oct 6, 2016