IP Library Granted Patent US 11,437,601
Granted Patent B2
US 11,437,601 · App. 14/804,872 · Granted Sep 6, 2022

Manufacturing method of light-emitting semiconductor device with a plurality of spacers between two substrates

Inventor: Toshiyuki Isa (Kanagawa, JP)
H01L51/525H01L27/3276H01L27/322H01L27/323H01L27/3246H01L51/5246H01L2227/323H01L2227/326
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,437,601
App. No.
14/804,872
Granted
Sep 6, 2022
Kind
B2
Abstract

A novel stacked structure that is highly convenient or reliable is provided. A method for manufacturing a novel stacked structure that is highly convenient or reliable is also provided. Furthermore, a novel semiconductor device is provided. The stacked structure includes first to fifth regions in this order. Each of the first to fifth regions includes a first base and a second base. The first region, the third region, and the fifth region each include a spacer that makes a predetermined distance between the first base and the second base.

Claims (72)

1. A process for manufacturing a semiconductor device, comprising:

preparing a first base on which a first partition and a second partition are formed;

forming a first spacer and a second spacer on the respective first and second partitions;

preparing a second base on which a first light blocking layer and a second light blocking layer are formed;

forming a bonding layer over the light blocking layers on the second base;

arranging the second base over the first base such that the first and the second light blocking layers overlap with the respective first and second partitions and with the respective first and second spacers provided therebetween;

setting a first environment, wherein the bonding layer is not in contact with the first base before arranging the first base and the second base in the first environment;

setting a second environment, wherein gas pressure in the second environment is higher than gas pressure in the first environment, and wherein the bonding layer is in contact with the first base and the second base after setting the second environment; and

curing the bonding layer;

wherein, during the manufacturing process, the semiconductor device comprises one region with a first region, a second region, and a third region within said one region,

wherein the first region is an active device region, the first region includes the first spacer,

wherein the second region is a terminal portion for accessing the active device, the second region does not include a spacer,

wherein the third region is a sacrificial border which surrounds the first and the second regions during the manufacturing process, the third region includes the second spacer, and

wherein the first and second spacers are configured to provide structural stability to said one region during the manufacturing process.

2. The method according to claim 1 , wherein the gas pressure in the second environment is an atmospheric pressure.

3. The method according to claim 1 , wherein the bonding layer is expanded between the first base and the second base after setting the second environment.

4. The method according to claim 1 , further comprising:

separating the third region from the second region.

5. The method according to claim 4 , further comprising:

exposing the terminal portion,

wherein the semiconductor device comprises a light-emitting element and a wiring electrically connected to the light-emitting element and the terminal portion.

6. The method according to claim 1 ,

wherein the first base comprises a first substrate, a first film, and a second film,

wherein the first spacer and the second spacer are formed over the second film,

wherein the first film comprises silicon, nitrogen and oxygen, and

wherein the second film comprises tungsten.

7. The method according to claim 1 ,

wherein the second base comprises a first substrate, a first film, and a second film,

wherein the first film comprises silicon, nitrogen and oxygen, and

wherein the second film comprises tungsten.

8. A process for manufacturing a semiconductor device, comprising:

preparing a first base on which a first partition and a second partition are formed;

forming a first spacer and a second spacer on the respective first and second partitions;

preparing a second base on which a first light blocking layer and a second light blocking layer are formed;

forming a bonding layer over the light blocking layers on the second base;

arranging the second base over the first base such that the first and the second light blocking layers overlap with the respective first and second partitions and with the respective first and second spacers provided therebetween;

setting a first environment, wherein the bonding layer is not in contact with the first base before arranging the first base and the second base in the first environment;

setting a second environment, wherein gas pressure in the second environment is higher than gas pressure in the first environment, and wherein the bonding layer is in contact with the first base and the second base after setting the second environment; and

curing the bonding layer,

wherein, during the manufacturing process, the semiconductor device comprises one region with a first region, a second region, and a third region within said one region,

wherein the bonding layer is included in the first region, the second region and the third region,

wherein the first region is an active device region, the first region includes the first spacer,

wherein the second region includes a terminal portion for accessing the active device, the second region does not include a spacer,

wherein the third region is a sacrificial border which surrounds the first and second regions during the manufacturing process, the third region includes the second spacer, and

wherein the first and second spacers are configured to provide structural stability to said one region during the manufacturing process.

9. The method according to claim 8 ,

wherein the first base comprises a first substrate, a first film, and a second film,

wherein the first spacer and the second spacer are formed over the second film,

wherein the first film comprises silicon, nitrogen and oxygen, and

wherein the second film comprises tungsten.

10. The method according to claim 8 ,

wherein the second base comprises a first substrate, a first film, and a second film,

wherein the first film comprises silicon, nitrogen and oxygen, and

wherein the second film comprises tungsten.

11. The method according to claim 8 , further comprising:

separating the third region from the second region.

12. A process method for manufacturing a semiconductor device, comprising:

preparing a first base on which a first partition and a second partition are formed;

forming a first spacer and a second spacer on the respective first and second partitions;

preparing a second base on which a first light blocking layer and a second light blocking layer are formed;

forming a bonding layer over the light blocking layers on the second base;

arranging the second base over the first base such that the first and the second light blocking layers overlap with the respective first and second partitions and with the respective first and second spacers provided therebetween;

setting a first environment, wherein the bonding layer is not in contact with the first base before arranging the first base and the second base in the first environment;

setting a second environment, wherein gas pressure in the second environment is higher than gas pressure in the first environment, and wherein the bonding layer is in contact with the first base and the second base after setting the second environment;

curing the bonding layer; and

exposing a terminal portion,

wherein, during the manufacturing process, the semiconductor device comprises one region with a first region, a second region, and a third region within said one region,

wherein the first region is an active device region, the first region includes the first spacer,

wherein the terminal portion is included in the second region for accessing the active device, the second region does not include a spacer,

wherein the third region is a sacrificial border which surrounds the first and second regions during the manufacturing process, the third region includes the second spacer

wherein the bonding layer is included in the first region, the second region and the third region, and

wherein the first and second spacers are configured to provide structural stability to said one region during the manufacturing process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2015
From: ISA, TOSHIYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 036144/0353 →
Priority Claims (1)
JP JP2014-151604 · Jul 25, 2014 · national
Continuity (1)
Related Publication 20160027967A1 · Jan 28, 2016
Cited By (1)
US 12,520,537