Granted Patent B2

US 10,372,544 · App. 14/805,072 · Granted Aug 6, 2019

Abstract

Claims (51)

1. A device comprising:

a plurality of memory cells;

an error detection circuit configured to detect at least one memory cell storing error data; and

a refresh control circuit comprising:

a register configured to store an error address corresponding to the at least one memory cell storing the error data, to provide the error address, and to control a refresh cycle of the error address;

a refresh counter capable of having a value corresponding to an address of a memory cell of the plurality of memory cells, the refresh counter configured to provide the value of the address of the memory cell;

a comparison circuit configured to receive, from the register, the error address, to receive, from the refresh counter, the value of the address of the memory cell, and to compare a portion of the error address stored in the register with a portion of the address of the memory cell, the portion of the error address being less than all of the error address, the portion of the address of the memory cell being less than all of the address of the memory cell, the comparison circuit further configured to output, when the error address is determined to be a matched error address based on a match between the portion of the error address stored in the register and the portion of the address of the memory cell, the matched error address; and

a selection control circuit configured to receive the matched error address, to select between the matched error address provided by the comparison circuit and the address of the refresh counter, and to output the matched error address when the portion of the error address is determined by the comparison circuit to be coincident with the portion of the value of the refresh counter.

2. The device as claimed in claim 1 ,

wherein the refresh control circuit is configured to perform a refresh operation on the at least one memory cell corresponding to the error address at a first refresh frequency and on a memory cell storing no-error data at a second refresh frequency, and

wherein the first refresh frequency is higher than the second refresh frequency.

3. The device as claimed in claim 1 ,

wherein the selection control circuit is configured to select and output the value when the portion of the error address is not coincident with the portion of the value of the refresh counter.

4. The device as claimed in claim 3 ,

wherein the portion of the error address is the address information excluding a most significant bit thereof.

5. The device as claimed in claim 3 ,

wherein the portion of the error address is the address information excluding two high-order bits thereof.

6. The device as claimed in claim 1 ,

wherein the comparison circuit is configured to compare the portion of the error address stored in the register with an address for a read or write operation on a memory cell of the plurality of memory cells.

7. The device as claimed in claim 6 ,

wherein the comparison circuit is configured to prohibit the register from storing the address for the read or write operation when the error address stored in the register is coincident with the address for read or write operation.

8. A device comprising:

a memory cell array device including first and second memory cell arrays, the first memory cell array comprising a plurality of first memory cells configured to store user data, the second memory cell array comprising a plurality of second memory cells configured to store verification data relating to the user data;

a verification circuit configured to receive the user data from the first memory cell array, to receive the verification data from the second memory cell array, to check whether the user data includes an error, by using the verification data, and to provide, when the user data includes the error, an error signal; and

a refresh control circuit configured to:

execute a refresh operation on the first memory cell array in order to increase a frequency of the refresh operation on a memory cell storing the error, wherein the refresh control circuit comprises an address register configured to receive, from the verification circuit, the error signal, wherein the address register is further configured to provide an address corresponding to the memory cell storing the error, wherein the refresh control circuit comprises a comparison circuit configured to receive the address, and to compare a portion of the address with a portion of an address of the plurality of first memory cells, wherein the portion of the address corresponding to the memory cell storing the error is less than all of the address corresponding to the memory cell storing the error, and wherein the portion of the address is less than all of the address,

activate a detection signal when the portion of the address corresponding to the memory cell storing the error is determined to be a matched error address based on a match between the portion of the address and the portion of the address of the plurality of first memory cells, and

output, to the memory cell array device, the matched error address, based on the activated detection signal, and

wherein the refresh operation is performed while a refresh counter completes a round of count value.

9. The device as claimed in claim 8 , wherein the refresh control circuit comprises a refresh counter capable of having the value corresponding to the address of the plurality of first memory cells.

10. The device as claimed in claim 9 ,

wherein the refresh control circuit comprises a selection control circuit configured to select and output the address corresponding to the memory cell storing the error data when the portion of the address is coincident with a portion of the value.

11. The device as claimed in claim 10 ,

wherein the selection control circuit is configured to select and output the value when the portion of the address is not coincident with the portion of the value.

12. The device as claimed in claim 11 ,

wherein the portion of the address is the address information excluding a most significant bit thereof.

13. The device as claimed in claim 8

wherein the refresh control circuit comprises a comparison circuit configured to compare the address stored in the address register with an address for a read or write operation on a memory cell of the first memory array.

14. A device comprising:

a plurality of word lines each coupled to a plurality of memory cells on which a refresh operation is performed in order to retain information stored therein;

a refresh control circuit configured to control the refresh operation; and

a verification circuit configured to receive data on at least first and second word lines among the plurality of word lines, to check the data on the at least first and second word lines among the plurality of word lines, and to provide, when the received data includes the error, an error signal,

wherein the refresh control circuit is configured to receive the error signal,

wherein, responsive to a comparison of a portion of an error address provided based on the received error signal with a portion of an address of the plurality of memory cells, the refresh control circuit is configured to change a frequency of the refresh operation on the first word line to a first frequency by outputting, from the verification circuit and at the first frequency, the error address that has the portion determined to match the portion of the address of the plurality of memory cells,

wherein the portion of the error address is less than all of the error address and the portion of the address of the plurality of memory cells is less than all of the address of the plurality of memory cells, and

wherein the error address output at the first frequency is associated with the first word line, and the refresh control circuit is further configured to keep a frequency of the refresh operation on the second word line which is clear from an error at a second frequency, and to perform a refresh operation while a refresh counter completes one round of count value updating.

15. The device as claimed in claim 14 ,

wherein the frequency of the refresh operation on the first word line is N times (N is power of two) more than the frequency of the refresh operation on the second word line, wherein N is a number power of two.

16. The device as claimed in claim 15 ,

wherein the refresh control circuit comprises a refresh counter configured to produce a count value corresponding to an address for the refresh operation, and

wherein the refresh control circuit is configured to perform the refresh operation on the first word line at least twice while the refresh counter completes a cycle of counting of the count value.

Assignments (8)