Method of thinning a wafer to provide a raised peripheral edge
View Patent ↗A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.
1. A method of forming a stacked wafer assembly, comprising:
manipulating at least one of first and second encapsulated components so as to assemble the first and second encapsulated components to form an assembly in which surfaces of the first and second encapsulated components are juxtaposed with one another, each of the first and second encapsulated components including an undiced semiconductor wafer comprising a plurality of semiconductor chips each being an integral portion of the wafer, the wafer having a semiconductor material extending continuously within the plurality of semiconductor chips and an active wafer surface defined by active surfaces of each of the semiconductor chips, an encapsulant extending outwardly from the semiconductor chips in directions parallel to the common active surface, a first area of each encapsulated component encompassing entire areas of the plurality of semiconductor chips of the respective encapsulated component having a reduced thickness, wherein a second area of each encapsulated component disposed beyond the first area has a thickness greater than the reduced thickness, the second area fully supporting the encapsulated component during the manipulating; and
processing the assembly to remove at least the second area of each encapsulated component such that the processed assembly has a thickness less than the sum of: the thicknesses of the encapsulated components within the respective second areas and the distance between the juxtaposed surfaces of the encapsulated components.
2. The method of claim 1 , wherein the processed assembly has a thickness less than or equal to the sum of: the reduced thicknesses of the first areas of the encapsulated components and the distance between the juxtaposed surfaces of the encapsulated components.
3. The method of claim 1 , wherein the manipulating is performed such that one of the juxtaposed surfaces is a common active surface of one of the first and second encapsulated components and one of the juxtaposed surfaces is a non-active surface of one of the first and second encapsulated components.
4. A method of forming a stacked wafer assembly, comprising:
manipulating at least one of first and second encapsulated components so as to assemble the first and second encapsulated components to form an assembly in which surfaces of the first and second encapsulated components are juxtaposed with one another, each of the first and second encapsulated components including a plurality of semiconductor chips each having an active surface disposed in a common plane defining a common active surface, and each of the semiconductor chips having a plurality of contacts at its respective active surface, an encapsulant extending outwardly from the semiconductor chips in directions parallel to the common active surface, a first area of each encapsulated component encompassing entire areas of the plurality of semiconductor chips of the respective encapsulated component having a reduced thickness, wherein a second area of each encapsulated component disposed beyond the first area has a thickness greater than the reduced thickness, the second area fully supporting the encapsulated component during the manipulating; wherein the manipulating is performed such that the juxtaposed surfaces are common active surfaces of the encapsulated components; and
processing the assembly to remove at least the second area of each encapsulated component such that the processed assembly has a thickness less than the sum of: the thicknesses of the encapsulated components within the respective second areas and the distance between the juxtaposed surfaces of the encapsulated components.
5. The method of claim 4 , wherein the assembling of the encapsulated components includes electrically interconnecting conductive elements of each of the first and second encapsulated components with one another.
6. The method of claim 5 , wherein the conductive elements of at least one of the first or second encapsulated components include interconnects disposed in the first area and extending in a direction of the thickness of such encapsulated component, wherein the assembling electrically connects the interconnects of the at least one encapsulated component with the conductive elements of another of the first or second encapsulated components.
7. The method of claim 5 , wherein at least one of the first or second encapsulated components includes an alignment surface disposed in the second area thereof, the manipulating being performed such that the alignment surface of the at least one encapsulated component aligns the at least one encapsulated component relative to at least one other of the encapsulated components.
8. The method of claim 7 , further comprising severing the assembly into a plurality of individual stacked assemblies, each stacked assembly including a first semiconductor chip severed from the first encapsulated component and a second semiconductor chip severed from the second encapsulated component, the second semiconductor chip stacked atop the first semiconductor chip.
9. A method of forming a stacked wafer assembly, comprising:
manipulating at least one of first and second encapsulated components so as to assemble the first and second encapsulated components to form an assembly in which surfaces of the first and second encapsulated components are juxtaposed with one another, each of the first and second encapsulated components including a plurality of semiconductor chips each having an active surface disposed in a common plane defining a common active surface, and each of the semiconductor chips having a plurality of contacts at its respective active surface, an encapsulant extending outwardly from the semiconductor chips in directions parallel to the common active surface, a first area of each encapsulated component encompassing entire areas of the plurality of semiconductor chips of the respective encapsulated component having a reduced thickness, wherein a second area of each encapsulated component disposed beyond the first area has a thickness greater than the reduced thickness, the second area fully supporting the encapsulated component during the manipulating; wherein the manipulating is performed such that the juxtaposed surfaces are non-active surfaces opposite from common active surfaces of each of the encapsulated components; and
processing the assembly to remove at least the second area of each encapsulated component such that the processed assembly has a thickness less than the sum of: the thicknesses of the encapsulated components within the respective second areas and the distance between the juxtaposed surfaces of the encapsulated components.