Array of cross point memory cells individually comprising a select device and a programmable device
A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture.
1. An array of cross point memory cells comprising:
spaced lower first lines, spaced upper second lines which cross the first lines, and an individual memory cell between the first lines and the second lines where such cross, the individual memory cells comprising:
a select device and a programmable device in series with each other, the select device being proximate and electrically coupled to one of the first or second lines, the programmable device being proximate and electrically coupled to one of the other of the first or second lines; and
the programmable device comprising:
a first pillar electrode elevationally over the one of the first lines, the first pillar electrode comprising elevationally-elongated conductive material and comprising a top and opposing sidewalls;
programmable material laterally outward of the opposing sidewalls of the first pillar electrode;
a second electrode outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode; and
one of the first pillar electrode or the second electrode being electrically coupled to the select device, the other of the first pillar electrode or the second electrode being electrically coupled to the one of the other of the first or second lines.
2. The array of claim 1 wherein the second electrodes of immediately adjacent of the memory cells along individual of the second lines are directly electrically coupled to one another.
3. The array of claim 2 wherein the second electrode comprises a conductive pillar, the immediately adjacent memory cells sharing one of the conductive pillars.
4. The array of claim 3 wherein the first pillar electrode has a maximum conductive material width that is greater than that of the conductive pillar laterally proximate the programmable material that is laterally outward of one of the opposing sidewalls of the first pillar electrode.
5. The array of claim 3 wherein the first pillar electrode has a maximum conductive material volume that is greater than that of the conductive pillar.
6. The array of claim 1 wherein the programmable material is elevationally over the top of the first pillar electrode.
7. The array of claim 6 wherein the programmable material comprises a continuous layer extending over the opposing sidewalls and the top of the first pillar electrode.
8. The array of claim 1 wherein the programmable material is beneath the second electrode between two immediately adjacent of the first lines.
9. The array of claim 1 wherein the second electrode is over the top of the first pillar electrode.
10. The array of claim 9 wherein the second electrode is of an upside-down U-shape in cross-section along its overlying second line.
11. The array of claim 1 wherein the first and second lines angle orthogonally relative one another.
12. An array of memory cells comprising:
spaced lower first lines, spaced upper second lines which cross the first lines, and an individual memory cell between the first lines and the second lines where such cross, the individual memory cells comprising:
a select device and a programmable device in series with each other, the select device being proximate and directly electrically coupled to one of the first lines, the programmable device being proximate and directly electrically coupled to one of the second lines; and
the programmable device comprising:
a first pillar electrode elevationally over and directly electrically coupled to the select device, the first pillar electrode comprising elevationally-elongated conductive material and comprising a top and opposing sidewalls;
programmable material laterally outward of the opposing sidewalls and elevationally over the top of the first pillar electrode; and
a second electrode outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode, the second electrode being directly electrically coupled to the one second line.
13. The array of claim 12 wherein the programmable material is continuous over multiple of the tops and sidewalls of multiple of the first pillar electrodes and beneath multiple of the second electrodes between immediately adjacent of the first lines.
14. An array of memory cells comprising:
spaced lower first lines, spaced upper second lines which cross the first lines, and an individual memory cell between the first lines and the second lines where such cross, the individual memory cells comprising:
a select device and a programmable device in series with each other, the select device being proximate and directly electrically coupled to one of the second lines, the programmable device being proximate and directly electrically coupled to one of the first lines; and
the programmable device comprising:
a first pillar electrode elevationally over and directly electrically coupled to the one first line, the first pillar electrode comprising a top and opposing sidewalls;
programmable material laterally outward of the opposing sidewalls and elevationally over the top of the first pillar electrode; and
a second electrode outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode, the second electrode being directly electrically coupled to the select device.
15. The array of claim 14 wherein the programmable material is continuous over multiple of the tops and sidewalls of multiple of the first pillar electrodes and beneath multiple of the second electrodes between immediately adjacent of the first lines.
16. The array of claim 14 wherein the first pillar electrode comprises elevationally-elongated conductive material.