Vertical NAND string multiple data line memory
View Patent ↗Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
1. An apparatus comprising:
a block of charge storage devices, the block having multiple rows of vertical strings of charge storage devices, each row of the multiple rows having multiple vertical strings, with each such vertical string having multiple charge storage devices coupled in series between a drain select gate and a source select gate, wherein each row is formed of a line of vertical strings of charge storage devices extending in a first direction;
at least four data lines associated with each row of vertical strings of charge storage devices and extending in the first direction of the row, the at least four data lines associated with each row of vertical strings extending at four respective vertically offset levels above the drain select gates of the vertical strings of that row,
wherein for individual rows of the multiple rows, each data line associated with that row is coupled to more than one of the multiple vertical strings in the row of vertical strings,
wherein adjacent vertical strings in an individual row of the multiple rows are coupled to different data lines; and
a common source coupled through respective source select gate transistors to the vertical strings of the multiple rows within the block.
2. The apparatus of claim 1 , wherein individual data lines of the multiple data lines comprise aluminum or copper.
3. The apparatus of claim 1 , wherein each vertical string of charge storage devices is associated with a semiconductor pillar, and wherein each drain select gate forms a drain cap on each respective pillar.
4. The apparatus of claim 3 , wherein each source select gate forms a source cap on each respective pillar.
5. The apparatus of claim 3 , further comprising a metal plug formed on and in contact with the drain cap.
6. An apparatus comprising:
a block of multiple vertical strings of charge storage devices, the vertical strings of charge storage devices arranged in multiple rows, each vertical string comprising multiple charge storage devices associated with a semiconductor pillar extending between a drain select gate transistor and a source select gate transistor, wherein each row is formed of a line of vertical strings of charge storage devices extending in a first direction;
at least four vertically offset tiers of data lines extending above each row, the data lines extending in the first direction, each tier including multiple data lines extending in the first direction, wherein each vertical string is coupled to one of the data lines,
wherein adjacent vertical strings within each row of the multiple rows are coupled to different data lines in different tiers extending over such row,
wherein adjacent vertical strings of different rows of the multiple rows are coupled to different data lines in different tiers, and
wherein each data line associated with a respective row is coupled to multiple vertical strings within the respective row;
wherein the source select gate transistors of the vertical strings in a respective row of the multiple rows each include a gate, and wherein the gates of the source select gate transistors in the respective row are coupled to a common select line; and
a common source coupled to the source select gate transistors of multiple vertical strings within the block.
7. The apparatus of claim 6 , wherein each vertical string of charge storage devices comprises:
a first dielectric at least partially surrounding the semiconductor pillar;
a floating gate at least partially surrounding the first dielectric;
a second dielectric at least partially surrounding the floating gate; and
a control gate at least partially surrounding the second dielectric.
8. The apparatus of claim 7 , further comprising a third dielectric between the second dielectric and the control gate.
9. The apparatus of claim 7 , wherein the control gate comprises a metal silicide control gate.
10. The apparatus of claim 9 , wherein the metal silicide comprises one of CoSi, TiSi, WSi, NiSi, TaSi, MoSi, or PtSi.
11. The apparatus of claim 6 , wherein each of the multiple vertical strings of charge storage devices is associated with a respective semiconductor pillar, and wherein the multiple vertically offset tiers of data lines extending above a respective row are formed over the semiconductor pillars of the vertical strings of the respective row.
12. An apparatus comprising:
a row of vertical strings of charge storage devices, each vertical string comprising multiple charge storage devices coupled in series, the multiple charge storage devices extending between a drain select gate transistor and a source select gate transistor, wherein the row extends in a first direction and includes at least four linearly arranged vertical strings of charge storage devices; and
at least four data lines associated with the row of vertical strings of charge storage devices, the at least four data lines also extending in the first direction and in respective at least four vertically offset tiers extending above the strings of the row, each of the at least four data lines coupled to multiple vertical strings in the row, wherein adjacent vertical strings along the row are coupled to different data lines;
wherein the source select gate transistors of the at least four vertical strings in the row each include a gate, and wherein the gates of the source select gate transistors in the row couple the respective string containing the source gate transistor to a common source.
13. The apparatus of claim 12 , wherein the at least four vertical strings in the row comprises at least eight vertical strings, and wherein each of the at least four data lines is connected to at least two strings in the row.
14. The apparatus of claim 13 , wherein each data line associated with the row of vertical strings is coupled in sequence to every fourth string of charge storage devices.
15. The apparatus of claim 12 , wherein the at least four data lines extend one above another, with a second data line extending above a first data line, a third data line extending above the second data line, and a fourth data line extending above the third data line.
16. The apparatus of claim 12 , wherein each charge storage device comprises a floating gate transistor.
17. The apparatus of claim 12 , wherein each charge storage device comprises a charge trap transistor.
18. The apparatus of claim 12 , wherein each drain select gate transistor forms a p-n junction with a respective pillar associated with a respective string of charge storage devices of the multiple vertical strings of charge storage devices.
19. The apparatus of claim 12 , wherein each source select gate transistor within a row forms a p-n junction with the respective pillar, the source select gate transistors in a row coupled to a common access line.
20. The apparatus of claim 19 , wherein each p-n junction couples the respective pillar to its respective data line of the at least four multiple data lines.