Backward compatibility by restriction of hardware resources
A new device executing an application on a new central processing unit (CPU), determines whether the application is for a legacy device having a legacy CPU. When the new device determines that the application is for the legacy device, it executes the application on the new CPU with selected available resources of the new device restricted to approximate or match a processing behavior of the legacy CPU.
1. A method, comprising:
with a new device executing an application on a new central processing unit (CPU), determining whether the application is for a legacy device having a legacy CPU; and
when the new device determines that the application is for the legacy device, executing the application on the new CPU with selected available resources of the new device restricted to match a processing behavior of the legacy CPU, wherein hardware of the new device is configured by firmware of the new CPU to restrict the selected available resources by reducing a usable portion of the selected available resources and wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes changing a size and an associativity of a micro-op cache, level 1 instruction cache or an instruction translation lookaside buffer cache hierarchy of the new CPU to match a size and an associativity for a corresponding a micro-op cache, level 1 instruction cache or an instruction translation lookaside buffer cache hierarchy of the legacy CPU and wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes: reducing a size of an indirect target array of the new CPU to match a size of a corresponding indirect target array of the legacy CPU.
2. The method of claim 1 , wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes reducing a size of a return address stack of the new CPU to match a size of a corresponding return address stack of the legacy CPU.
3. The method of claim 1 , wherein executing the application on the new CPU with selected available resources of the new device restricted includes reducing a size of a branch target buffer of the new CPU to match a size of a corresponding branch target buffer of the legacy CPU.
4. The method of claim 1 , wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes reducing a size of a queue of the new CPU to match a size of a corresponding queue of the legacy CPU.
5. The method of claim 4 , wherein the queue of the new CPU is a retirement queue or a scheduling queue.
6. The method of claim 1 , wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes reducing a size a register bank of the new CPU to match a corresponding size of a register bank of the legacy CPU.
7. The method of claim 6 , wherein the register bank of the new CPU is a Single Instruction Multiple Data (SIMD) physical register bank or a General Purpose (GP) physical register bank.
8. The method of claim 1 , wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes reducing a number of usable execution units of the new CPU to match an available number of corresponding execution units of the legacy CPU.
9. The method of claim 8 , wherein the execution units of the new CPU include Arithmetic Logic Units (ALU), Address Generation Units (AGU) or Single Instruction Multiple Data (SIMD) pipes.
10. The method of claim 1 , wherein executing the application on the new CPU with selected available resources of the new CPU restricted further includes changing a size or associativity of a cache of the new CPU other than the micro-op cache, the level 1 instruction cache or the instruction translation lookaside buffer cache hierarchy of the new CPU to match a corresponding size or associativity of a corresponding cache of the legacy CPU.
11. The method of claim 10 , wherein the cache is an instruction-related cache other than the level 1 instruction cache.
12. The method of claim 10 , wherein the cache is a data translation lookaside buffer (DTLB) cache hierarchy or a level 1 data cache.
13. The method of claim 1 wherein associativity of the instruction translation lookaside buffer cache hierarchy of the new CPU is changed to match the associativity of the corresponding instruction translation lookaside buffer cache hierarchy of the legacy CPU.
14. The method of claim 1 wherein the new device is a variant or a more advanced version of the legacy device.
15. A system, comprising,
a new central processing unit (CPU) configured to execute instructions of an application, the new CPU having logic units configured to determine whether the application is for a legacy device having a legacy CPU, and execute the application with selected available resources of the new CPU restricted to match a processing behavior of the legacy CPU when the application is for the legacy device, wherein hardware of the new CPU is configured by firmware of the new CPU to restrict the selected available resources by reducing a usable portion of the selected available resources and wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes changing a size and an associativity of a micro-op cache, level 1 instruction cache or an instruction translation lookaside buffer cache hierarchy of the new CPU to match a size and an associativity for a corresponding a micro-op cache, level 1 instruction cache or an instruction translation lookaside buffer cache hierarchy of the legacy CPU and wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes: reducing a size of an indirect target array of the new CPU to match a size of a corresponding indirect target array of the legacy CPU.
16. The system of claim 15 , wherein the selected available resources of the new CPU are restricted by reducing a size of a return address stack of the new CPU to match a size of a corresponding return address stack of the legacy CPU.
17. The system of claim 15 , wherein the selected available resources of the new CPU are restricted by reducing a size of a branch target buffer of the new CPU to match a size of a corresponding branch target buffer of the legacy CPU.
18. The system of claim 15 , wherein the selected available resources of the new CPU are restricted by reducing a size of a queue of the new CPU to match a size of a corresponding queue of the legacy CPU.
19. The system of claim 18 , wherein the queue of the new CPU is a retirement queue or a scheduling queue.
20. The system of claim 15 , wherein the selected available resources of the new CPU are restricted by reducing a size a register bank of the new CPU to match a corresponding size of a register bank of the legacy CPU.
21. The system of claim 20 , wherein the register bank of the new CPU is a Single Instruction Multiple Data (SIMD) physical register bank or a General Purpose (GP) physical register bank.
22. The system of claim 15 , wherein the selected available resources of the new CPU are restricted by reducing a number of usable execution units of the new CPU to match an available number of corresponding execution units of the legacy CPU.
23. The system of claim 22 , wherein the execution units of the new CPU include Arithmetic Logic Units (ALU), Address Generation Units (AGU) or Single Instruction Multiple Data (SIMD) pipes.
24. The system of claim 15 , wherein the selected available resources of the new CPU restricted are further restricted by changing an associativity of a cache of the new CPU other than the micro-op cache, the level 1 instruction cache or the instruction translation lookaside buffer cache hierarchy of the new CPU to match a corresponding size or associativity of a corresponding cache of the legacy CPU.
25. The system of claim 24 , wherein the cache is an instruction-related cache other than the level 1 instruction cache.
26. The system of claim 24 , wherein the cache is a data translation lookaside buffer (DTLB) cache hierarchy or a level 1 data cache.
27. The system of claim 15 wherein the system is a variant or a more advanced version of the legacy device.
28. A non-transitory computer readable medium having executable instructions embodied therein, the instructions being configured to implement a method upon execution of the instructions, the method comprising:
with a new device executing an application on a new central processing unit (CPU), determining whether the application is for a legacy device having a legacy CPU; and
when the new device determines that the application is for the legacy device executing the application on the new CPU with selected available resources of the new device restricted to match a processing behavior of the legacy CPU, wherein hardware of the new device is configured by firmware of the new CPU to restrict the selected available resources by reducing a usable portion of the selected available resources and wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes changing a size and an associativity of a micro-op cache, level 1 instruction cache or an instruction translation lookaside buffer cache hierarchy of the new CPU to match a size and an associativity a micro-op cache, level 1 instruction cache or an instruction translation lookaside buffer cache hierarchy of the legacy CPU and wherein executing the application on the new CPU with selected available resources of the new CPU restricted includes: reducing a size of an indirect target array of the new CPU to match a size of a corresponding indirect target array of the legacy CPU.
29. The non-transitory computer readable medium of claim 28 wherein the new device is a variant or a more advanced version of the legacy device.