Semiconductor memory device capable of reducing chip size
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
1. A semiconductor memory device comprising:
a plurality of memory cells of a first conductivity type, wherein the plurality of memory cells are connected to a source line;
a plurality of bit lines connected to the plurality of memory cells;
a plurality of first bit line select transistors of the first conductivity type which are connected at one end to the source line, and which select a bit line from the plurality of bit lines and connect the selected bit line to a sense amplifier;
a plurality of second bit line select transistors of the first conductivity type which select an unselected bit line of the plurality of bit lines and supply a potential to the unselected bit line;
a first well of the first conductivity type which is formed in a substrate; and
a second well of a second conductivity type which is formed in the first well,
wherein the plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and
wherein the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged between the sense amplifier and the plurality of the memory cells.
2. The device according to claim 1 , wherein the plurality of the second bit line select transistors supply a potential of the source line to the unselected bit line.
3. The device according to claim 1 , wherein the plurality of memory cells are connected to a plurality of source lines, respectively, and the plurality of second bit line select transistors are arranged at longitudinal central portions of the plurality of bit lines.
4. The device according to claim 3 , wherein the plurality of second bit line select transistors supply a potential of the plurality of source lines to the unselected bit line.
5. The device according to claim 1 , wherein the plurality of memory cells form NAND strings.
6. The device according to claim 1 , further comprising:
an active region of the pair of first bit line select transistors, which is formed separately from one end of each of a first bit line and a second bit line;
a first interconnected layer and a second interconnect layer which are arranged at a pitch twice a pitch of the first bit line and the second bit line and connected to the first bit line and the second bit line, respectively, the first interconnect layer and the second interconnect layer being located under the first bit line and the second bit line;
a third interconnect layer which is arranged along the first interconnect layer at the same level as that of the first bit line and the second bit line, and connected to the sense amplifier;
a first contact which connects the first interconnect layer to the active region;
a second contact which connects the second interconnect layer to the active region; and
a third contact which connects the third interconnect layer to the active region serving as a connection node of the pair of first bit line select transistors.
7. The device according to claim 1 , further comprising:
a plurality of select transistors adjacent to one of the plurality of memory cells,
wherein each of the bit lines is connected to one of the plurality of select transistors.
8. The device according to claim 1 , wherein the potential to the unselected bit line is a source line voltage.
9. A semiconductor memory device comprising:
a plurality of memory cells of a first conductivity type which form a first NAND string and a second NAND string, wherein one end of the NAND string and the second NAND string is connected to a source line;
a first bit line to which the other end of the first NAND string is connected;
a second bit line to which the other end of the second NAND string is connected;
a pair of first bit line select transistors of the first conductivity type which are connected at one end to the first source line, and which select a bit line from the first bit line and the second bit line and connect the selected bit line to a sense amplifier;
a pair of second bit line select transistors of the first conductivity type which select an unselected bit line of the first bit line and the second bit line and supply a potential to the unselected bit line;
a first well of the first conductivity type which is formed in a substrate; and
a second well of a second conductivity type which is formed in the first well,
wherein the first NAND string, the second NAND string, the first bit line select transistors, and the second bit line select transistors are formed in the second well, and
wherein the first bit line select transistors and the second bit line select transistors are arranged between the sense amplifier and the plurality of memory cells of the plurality of bit lines.
10. The device according to claim 9 , wherein a connection node of the pair of second bit line select transistors is connected to the source line, and the pair of second bit line select transistors supply a potential of the second source line to the unselected bit line.
11. The device according to claim 9 , further comprising:
a third NAND string connected to the first bit line; and
a fourth NAND string connected to the second bit line.
12. The device according to claim 11 , wherein
an end of each of the third NAND string and the fourth NAND string is connected to a second source line, and
the pair of the second bit line select transistors are arranged at longitudinal central portions of the first bit line and the second bit line.
13. The device according to claim 12 , wherein the pair of second bit line select transistors have a connection node connected to the first source line and the second source line, and supply a potential of the first source line and the second source line to the unselected bit line.
14. The device according to claim 9 , further comprising:
an active region of the pair of first bit line select transistors, which is formed separately from one end of each of the first bit line and the second bit line;
a first interconnect layer and a second interconnect layer which are arranged at a pitch twice a pitch of the first bit line and the second bit line and connected to the first bit line and the second bit line, respectively, the first interconnect layer and the second interconnect layer being located under the first bit line and the second bit line;
a third interconnect layer which is arranged along the first interconnect layer at the same level as that of the first bit line and the second bit line, and connected to the sense amplifier;
a first contact which connects the first interconnect layer to the active region;
a second contact which connects the second interconnect layer to the active region; and
a third contact which connects the third interconnect layer to the active region serving as a connection node of the pair of first bit line select transistors.
15. The device according to claim 9 , further comprising:
a plurality of select transistors adjacent to the first NAND string or the second NAND string,
wherein each of the bit lines is connected to one of the plurality of select transistors.
16. The device according to claim 9 , wherein the potential to the unselected bit line is a source line voltage.