IP Library Granted Patent US 9,563,570
Granted Patent B2
US 9,563,570 · App. 14/813,444 · Granted Feb 7, 2017

System and methods exchanging data between processors through concurrent shared memory

Inventors: Brent S. Baxter (Hillsboro, OR); Clifford D. Hall (Orangeville, CA); Prashant Sethi (Folsom, CA); William H. Clifford (Gig Harbor, WA)
Assignee: Intel Corporation
G06F12/1009G06F12/0238G06F12/109G06F2212/65
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,563,570
App. No.
14/813,444
Granted
Feb 7, 2017
Kind
B2
Abstract

A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Claims (30)

1. An apparatus, comprising:

a first processing unit, the first processing unit to generate a pointer to a virtual memory address;

a second processing unit coupled to the first processing unit, the second processing unit to receive the pointer from the first processing unit; and

control logic separate from the second processing unit to translate the virtual memory address to a physical memory address based on a page table mapping, the control logic to share the page table mapping with the second processing unit, wherein based on the page table mapping, the second processing unit to access the physical memory address with the pointer.

2. The apparatus of claim 1 , further comprising a memory, the memory including the physical memory address.

3. The apparatus of claim 1 , wherein to share the page table mapping with the second processing unit the control logic to copy at least one of a page directory, or at least one page table for use by the second processing unit to access the physical memory address with the pointer.

4. The apparatus of claim 1 , wherein, based on accessing the physical memory address with the pointer, the second processor to process media information.

5. The apparatus of claim 4 , wherein the media information comprises at least one of video information or audio information.

6. The apparatus of claim 1 , wherein the first processing unit and the second processing unit are to share the page table mapping.

7. The apparatus of claim 1 , wherein the first processing unit is to access the physical memory address by use of the pointer based on the page table mapping.

8. A method, comprising:

generating, at a first processor, a pointer to a virtual memory address, wherein the virtual memory address is associated with a physical memory address according to a page table mapping;

receiving, at a second processor, the pointer from the first processor; and

accessing, at the second processor based on the page table mapping, the physical memory address with the pointer, the physical memory address for a memory communicatively coupled with and separate from the first and second processors.

9. The method of claim 8 , wherein the page table mapping comprises a page directory and at least one page table, the method further comprising storing the page directory and the at least one page table in the memory.

10. The method of claim 8 , further comprising based on accessing the physical memory address with the pointer, processing media information at the second processor.

11. The method of claim 10 , wherein the media information comprises at least one of video information or audio information.

12. The method of claim 8 , wherein the first processor and the second processor share the page table mapping.

13. The method of claim 8 , comprising:

accessing, at the first processor the physical memory address for the memory using the pointer and based on the page table mapping.

14. At least one non-transitory machine readable medium having stored thereon one or more instructions that, when executed by a computing device, causes the computing device to:

generate, at a first processor, a pointer to a virtual memory address, wherein the virtual memory address is associated with a physical memory address according to a page table mapping;

receive, at a second processor, the pointer from the first processor; and

access, at the second processor based on the page table mapping, the physical memory address with the pointer, the physical memory address for a memory communicatively coupled with and separate from the first and second processors.

15. The at least one non-transitory machine readable medium of claim 14 , wherein the page table mapping comprises a page directory and at least one page table, the at least one machine readable medium further having stored thereon one or more additional instructions that, when executed by the computing device, causes the computing device to store the page directory and the at least one page table in the memory.

16. The at least one non-transitory machine readable medium of claim 14 , further having stored thereon one or more additional instructions that, when executed by the computing device, causes the computing device to process media information at the second processor based on accessing the physical memory address with the pointer.

17. The at least one non-transitory machine readable medium of claim 16 , wherein the media information comprises at least one of video information or audio information.

18. The at least one non-transitory machine readable medium of claim 14 , wherein the first processor and the second processor are to share the page table mapping.

19. The at least one non-transitory machine readable medium of claim 14 , having stored thereon one or more instructions that, when executed by a computing device, cause the computing device to:

access, at the first processor the physical memory address for the memory by use of the pointer and based on the page table mapping.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2017
From: BAXTER, BRENT S.; SETHI, PRASHANT; HALL, CLIFFORD D.; CLIFFORD, WILLIAM H.
To: INTEL CORPORATION
Reel/Frame 041483/0734 →
Continuity (4)
Continuation 14079843 · Nov 14, 2013
Continuation 12349080 · Jan 6, 2009
Continuation 11022503 · Dec 22, 2004
Related Publication 20160188484A1 · Jun 30, 2016