IP Library Granted Patent US 9,502,381
Granted Patent B2
US 9,502,381 · App. 14/817,502 · Granted Nov 22, 2016

Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 9,502,381
App. No.
14/817,502
Granted
Nov 22, 2016
Kind
B2
Abstract

Embodiments of the present disclosure provide a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device. The semiconductor device comprises: a semiconductor die; an electrical isolation layer formed on a surface of the semiconductor die; a substrate; and a non-conductive adhesive layer disposed between the electrical isolation layer and the substrate, so as to adhere the electrical isolation layer to the substrate.

Claims (16)

1. A semiconductor device, comprising:

a semiconductor die;

an electrical isolation layer formed on a surface of the semiconductor die, the electrical isolation layer abutting the semiconductor die and having a Rockwell hardness E scale value of at least 52;

a substrate; and

a non-conductive adhesive layer disposed between the electrical isolation layer and the substrate, so as to adhere the electrical isolation layer to the substrate, the electrical isolation layer being harder than the adhesive layer.

2. The semiconductor device according to claim 1 , wherein the semiconductor die comprises a bonding pad, the bonding pad being disposed at another surface of the semiconductor die opposite to the surface.

3. The semiconductor device according to claim 2 , further comprising a lead, the lead being connected to the bonding pad using a bonding wire.

4. The semiconductor device according to claim 1 , further comprising:

a further semiconductor die; and

a conductive adhesive layer configured to adhere the further semiconductor die to the substrate.

5. The semiconductor device according to claim 1 , wherein the non-conductive adhesive layer comprises a die attach film or an adhesive glue.

6. The semiconductor device according to claim 1 , wherein the electrical isolation layer is a molding layer or a spin-coated layer.

7. The semiconductor device according to claim 1 wherein a molding compound encapsulates the semiconductor device to form a semiconductor package.

8. The semiconductor device according to claim 1 , wherein the electrical isolation layer has a Rockwell hardness E scale value in a range of 52-99.

9. The semiconductor device according to claim 1 , the electrical isolation layer has a Rockwell hardness E scale value in a range of 69-120.

10. The semiconductor device according to claim 1 , wherein the electrical isolation layer is formed from a plastic sheet.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068433/0970 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2015
From: LUAN, JING-EN
To: STMICROELECTRONICS PTE LTD
Reel/Frame 036250/0885 →