Apparatus and method for precharging a load
An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.
1. An apparatus for pre-charging, the apparatus comprising:
an output stage of an amplifier comprising:
a first transistor;
a second transistor;
a first output node connected to the first and second transistors; and
at least one compensation capacitor; and
one or more output stage switches configured to connect or disconnect at least part of the output stage from an earlier stage of the amplifier, wherein the earlier stage comprises an amplifying stage being earlier in a signal path than the output stage,
wherein the at least part of the output stage is configured to precharge at least one switched capacitive load substantially while the at least part of the output stage is disconnected from the earlier stage.
2. The apparatus of claim 1 , wherein the at least part of the output stage is configured to precharge the at least one switched capacitive load for a first precharging duration within a first switch phase of the at least one switched capacitive load.
3. The apparatus of claim 2 , wherein the at least part of the output stage is configured to precharge the at least one switched capacitive load for a second precharging duration within a second switch phase of the at least one switched capacitive load.
4. The apparatus of claim 1 , wherein the at least one switched capacitive load is an input capacitor of an analog-to-digital converter (ADC).
5. The apparatus of claim 1 , wherein the earlier stage of the amplifier is configured to autozero when the output stage of the amplifier precharges the at least one switched capacitive load.
6. The apparatus of claim 1 , wherein the at least one compensation capacitor is arranged as a Miller capacitor.
7. The apparatus of claim 1 , wherein the output stage of the amplifier further comprises:
a third transistor;
a fourth transistor; and
a second output node connected to the third and fourth transistors.
8. The apparatus of claim 7 , wherein the at least part of the output stage is configured to precharge two switched capacitive loads substantially during the at least part of the output stage is disconnected from the earlier stage.
9. The apparatus of claim 7 , wherein at least part of the output stage is always connected to the earlier stage.
10. The apparatus of claim 7 , wherein the second output node is further connected to an input of the amplifier.
11. The apparatus of claim 9 , wherein the at least part of the output stage is configured to precharge two switched capacitive loads substantially during the at least part of the output stage is disconnected from the earlier stage.
12. A method of precharging at least one switched capacitive load connected to at least one output of an amplifier, the method comprising:
disconnecting at least part of an output stage of the amplifier from an earlier stage of the amplifier for a first precharging duration within a first switch phase of the at least one switched capacitive load, wherein the earlier stage comprises an amplifying stage;
connecting an output node of the amplifier to the at least one switched capacitive load for the duration of the first switch phase of the at least one switched capacitive load; and
reconnecting the output stage of the amplifier to the earlier stage of the amplifier for a first fine settling duration after the first precharging duration,
wherein the output stage comprises a first transistor and a second transistor and is compensated with at least one capacitor.
13. The method of claim 12 , further comprising:
disconnecting the at least part of the output stage of the amplifier from the earlier stage of the amplifier for a second precharging duration after the first fine settling duration within a second switch phase of the at least one switched capacitive load;
disconnecting the output of the amplifier from the at least one switched capacitive load for the duration of the second switch phase of the at least one switched capacitive load;
connecting the output of the amplifier to another at least one switched capacitive load for the duration of the second switch phase of the at least one switched capacitive load; and
reconnecting the output stage of the amplifier to the first earlier stage of the amplifier for a second fine settling duration after the second precharging duration.
14. The method of claim 12 , further comprising autozeroing the earlier stage of the amplifier for the first precharging duration.
15. The method of claim 12 , wherein the at least one capacitor is arranged as a Miller capacitor.