Printed circuit board and semiconductor package
Provided is a printed circuit board including a first conductive layer including a first conductive layer including a recessed portion, a protruding portion disposed at a higher level than that of the recessed portion, and a connecting portion connecting the recessed portion with the protruding portion. A second conductive layer is disposed above the recessed portion of the first conductive layer. A core layer is disposed between the first conductive layer and the second conductive layer. An upper solder resist layer is disposed on the second conductive layer. The upper solder resist layer exposes at least a portion of the protruding portion. A lower solder resist layer is disposed below the first conductive layer.
1. A printed circuit board, comprising:
a first conductive layer including a recessed portion, a protruding portion disposed at a higher level than that of the recessed portion, and a connecting portion connecting the recessed portion with the protruding portion;
a second conductive layer disposed above the recessed portion of the first conductive layer;
a core layer disposed between the first conductive layer and the second conductive layer;
an upper solder resist layer disposed on the second conductive layer, wherein the upper solder resist layer exposes at least a portion of the protruding portion; and
a lower solder resist layer disposed below the first conductive layer.
2. The printed circuit board of claim 1 , wherein a level of a top surface of the protruding portion is substantially equal to or higher than a level of a top surface of the second conductive layer.
3. The printed circuit board of claim 1 , wherein a level of a top surface of the protruding portion is substantially equal to or lower than a level of a top surface of the upper solder resist layer.
4. The printed circuit board of claim 1 , wherein a top surface of the recessed portion is parallel to a top surface of the protruding portion.
5. The printed circuit board of claim 1 , wherein the second conductive layer comprises a pattern having a same shape as a shape of the recessed portion of the first conductive layer.
6. The printed circuit board of claim 1 , further comprising outer connection solder balls penetrating the lower solder resist layer, wherein the outer connection solder balls are electrically connected to the first conductive layer.
7. A semiconductor package, comprising:
a printed circuit board;
a semiconductor chip disposed on the printed circuit board; and
a mold layer encapsulating the semiconductor chip,
wherein the printed circuit board comprises:
a first conductive layer including a recessed portion, a protruding portion disposed at a higher level than that of the recessed portion, and a connecting portion connecting the recessed portion with the protruding portion;
a second conductive layer disposed above the recessed portion of the first conductive layer;
a core layer disposed between the first conductive layer and the second conductive layer;
an upper solder resist layer disposed on the second conductive layer, wherein the upper solder resist layer exposes at least a portion of the protruding portion; and
a lower solder resist layer disposed below the first conductive layer,
wherein the semiconductor chip is electrically connected to the protruding portion of the first conductive layer through chip bumps.
8. The semiconductor package of claim 7 , wherein a level of a top surface of the protruding portion is substantially equal to or higher than a level of a top surface of the second conductive layer.
9. The semiconductor package of claim 7 , wherein a top surface of the recessed portion is parallel to a top surface of the protruding portion.
10. The semiconductor package of claim 7 , wherein the second conductive layer comprises a wiring pattern having a same shape as a shape of the recessed portion of the first conductive layer.
11. The semiconductor package of claim 7 , wherein the printed circuit board further comprises outer connection solder balls penetrating the lower solder resist layer, wherein the outer connection solder balls are electrically connected to the first conductive layer.
12. The semiconductor package of claim 7 , further comprising heat-dissipation bumps disposed on the second conductive layer, wherein the heat-dissipating bumps are in contact with the semiconductor chip and the second conductive layer through the upper solder resist layer.
13. The semiconductor package of claim 7 , wherein the printed circuit board further comprises:
a third conductive layer disposed between the first conductive layer and the lower solder resist layer;
a fourth conductive layer disposed between the first and third conductive layers;
a first insulating layer disposed between the third and fourth conductive layers; and
a second insulating layer disposed between the first and fourth conductive layers.
14. The semiconductor package of claim 13 , wherein the second and fourth conductive layers are respectively connected to power and ground pads of the semiconductor chip, and wherein the first conductive layer is connected to signal pads of the semiconductor chip.