IP Library Granted Patent US 9,690,509
Granted Patent B2
US 9,690,509 · App. 14/821,940 · Granted Jun 27, 2017

Computer instructions for limiting access violation reporting when accessing strings and similar data structures

Inventors: Michael Gschwind (Chappaqua, NY); Brett Olsson (Cary, NC); Raul E. Silvera (Dublin, CA)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F3/0622G06F3/0659G06F3/0673G06F9/3887G06F12/121G06F12/1425G06F13/24G06F12/1458G06F2212/1052G06F2212/69
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Quick Facts
Patent No.
US 9,690,509
App. No.
14/821,940
Granted
Jun 27, 2017
Kind
B2
Abstract

Embodiments are directed to a computer implemented method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block. The method includes initiating, by a processor, an access of the data frame. The method further includes accessing, by the processor, the first portion of the data frame. The method further includes, based at least in part on a determination that the processor does not have access to the second memory block, accessing at least one default character as a replacement for accessing the second portion of the data frame.

Claims (22)

1. A computer implemented method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block, the method comprising:

initiating, by a processor, an access of the data frame;

accessing, by said processor, the first portion of the data frame;

based at least in part on a determination that said processor does not have access to the second memory block, accessing at least one valid default character as a replacement for accessing the second portion of the data frame; and

based at least in part on the determination that said processor does not have access to the second memory block, reading the first portion of the data frame, reading the at least one valid default character, and loading the first portion of the data frame and the at least one valid default character to a target location in order to process the first portion of the data frame and the at least one valid default character as a valid data frame.

2. The computer implemented method of claim 1 , wherein:

the data frame comprises a null-terminated string having an indeterminate length;

said null-terminated string comprises a data portion and at least one terminator character; and

said at least one terminator character indicates a termination of said null-terminated string.

3. The computer implemented method of claim 1 further comprising:

based at least in part on a determination that said processor has access to the second memory block, accessing, by said processor, the second portion of the data frame.

4. The computer implemented method of claim 1 , wherein:

said target location comprises a target register; and

said at least one valid default character loaded in said target register represents a termination of a data portion of said data frame.

5. The computer implemented method of claim 4 , wherein said loading the first portion of the data frame and said loading said at least one valid default character comprise a serial operation.

6. The computer implemented method of claim 4 , wherein said loading the first portion of the data frame and said loading said at least one valid default character comprise a parallel operation.

7. The computer implemented method of claim 6 , wherein said parallel operation comprises a single instruction multiple data (SIMD) operation.

8. The computer implemented method of claim 1 , wherein:

the first memory block comprises a first memory page; and

the second memory block comprises a second memory page.

9. The computer implemented method of claim 1 , wherein said determination that said processor does not have access to the second memory block comprises detecting an access protection violation.

10. The computer implemented method of claim 9 , wherein said detecting said access protection violation comprises detecting that a predetermined bit of an interrupt status register has been set.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2015
From: GSCHWIND, MICHAEL; OLSSON, BRETT; SILVERA, RAUL E.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036287/0925 →
Continuity (2)
Continuation 14583970 · Dec 29, 2014
Related Publication 20160188496A1 · Jun 30, 2016