Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of m transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.
1. A device for storing data, the device comprising:
a plurality of transistors each of which is capable of storing charge, wherein each of the plurality of transistors comprises a gate, a source, and a drain;
a plurality of electrical connections coupled to the source of each of the plurality of transistors;
a plurality of electrical connections coupled to the drain of each of the plurality of transistors;
wherein the data stored in the device corresponds to a sum of charges stored in each of the plurality of transistors.
2. A device as in claim 1 , further comprising electrical connections between the gates of each of the plurality of transistors.
3. The device as in claim 1 further comprising a non-transitory computer readable medium embodying information indicative of instructions for causing one or more processors to perform operations comprising:
generating a code word having a plurality of symbols selected from a set of symbols; and
storing each of the plurality of symbols in a respective data storage location of the device, wherein at least one data storage location comprises the plurality of transistors.
4. The device as in claim 3 , wherein the plurality of transistors comprise floating gate transistors.
5. The device as in claim 1 further comprising a non-transitory computer readable medium embodying information indicative of instructions for causing one or more processors to perform operations comprising:
defining a predetermined rank configuration (d 1 , d 2 . . . d n ), wherein d is the number of cells in the i th rank;
receiving a new multi-permutation defined by v=[v 1 , v 2 , . . . , v n ]∈S n that fits the predetermined rank configuration; and
in response to receiving the new multi-permutation, initiate a process to add charge to each cell in a plurality of memory locations comprising the plurality of transistors such that the cells represent the new multi-permutation.
6. The device as in claim 1 further comprising a non-transitory computer readable medium embodying information indicative of instructions for causing one or more processors to perform operations comprising:
determining a sequential order of an initial analog level of a stored value in each cell of a plurality of cells in the device, wherein the sequential order is defined as a value x comprising
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7. The device as in claim 1 further comprising a non-transitory computer readable medium embodying information indicative of instructions for causing one or more processors to perform operations comprising:
defining a predetermined rank configuration (d 1 , d 2 . . . d n ), wherein d i is the number of cells in the i th rank;
receiving a new multi-permutation defined by v=[v 1 , v 2 , . . . , v n ]∈S n that fits the predetermined rank configuration;
retaining analog levels of cells of a rank n in v; and
programming cells, comprising the plurality of transistors, of rank i in v for i=n−1, n−2, . . . , 1 such that analog levels of cells in a rank i are all higher than analog levels of cells of rank i+1 in v by at least a minimum rank differentiation.
8. The device as in claim 7 , wherein the analog level in each of the cells corresponds to a stored charge in a floating gate transistor.
9. The device as in claim 1 further comprising:
an interface that receives a new data set for a rank of a plurality of ranks to be stored in a memory comprising a plurality of cells;
a processor configured to perform operations of:
generating a code word having a plurality of symbols selected from a set of symbols; and
storing each of the plurality of symbols in a respective data storage location of the device, wherein at least one data storage location comprises the plurality of transistors.
10. The device as in claim 9 , wherein the plurality of transistors comprise floating gate transistors.
11. The device as in claim 1 further comprising:
an interface that receives a new data set for a rank of a plurality of ranks to be stored in a memory comprising a plurality of cells;
a processor configured to perform operations of:
defining a predetermined rank configuration (d 1 , d 2 . . . d n ), wherein d i is the number of cells in the i th rank;
receiving a new multi-permutation defined by v=[v 1 , v 2 , . . . , v n ]∈S n that fits the predetermined rank configuration; and
in response to receiving the new multi-permutation, initiate a process to add charge to each cell in a plurality of memory locations comprising the plurality of transistors such that the cells represent the new multi-permutation.
12. The device as in claim 1 further comprising:
an interface that receives a new data set for a rank of a plurality of ranks to be stored in a memory comprising a plurality of cells;
a processor configured to perform operations of:
determining a sequential order of an initial analog level of a stored value in each cell of a plurality of cells comprising the plurality of transistors in the device, wherein the sequential order is defined as a value x comprising
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13. The device as in claim 1 further comprising:
an interface that receives a new data set for a rank of a plurality of ranks to be stored in a memory comprising a plurality of cells comprising the plurality of transistors;
a processor configured to perform operations of:
defining a predetermined rank configuration (d 1 , d 2 . . . d n ), wherein d i is the number of cells in the i th rank;
receiving a new multi-permutation defined by v=[v 1 , v 2 , . . . , v n ]∈S n that fits the predetermined rank configuration;
retaining analog levels of cells of a rank n in v; and
programming cells of rank i in v for i=n−1, n−2, . . . , 1 such that analog levels of cells in a rank i are all higher than analog levels of cells of rank i+1 in v by at least a minimum rank differentiation.
14. The device as in claim 13 , wherein the analog level in each of the cells corresponds to a stored charge in a floating gate transistor.
15. The device as in claim 1 further comprising:
a memory configured to store data values:
a memory controller that is configured to store the data values in the memory by performing operations comprising:
generating a code word having a plurality of symbols selected from a set of symbols; and
storing each of the plurality of symbols in a data storage location of the device, wherein each data storage location comprises the plurality of transistors.
16. The device as in claim 15 , wherein the parallel connected devices comprise floating gate transistors.
17. The device as in claim 1 further comprising:
a memory configured to store data values:
a memory controller that is configured to store the data values in the memory by performing operations comprising:
defining a predetermined rank configuration (d 1 , d 2 . . . d n ), wherein d i is the number of cells in the i th rank;
receiving a new multi-permutation defined by v=[v 1 , v 2 , . . . , v n ]∈S n that fits the predetermined rank configuration; and
in response to receiving the new multi-permutation, initiate a process to add charge to each cell in a plurality of memory locations such that the plurality of cells, which comprise the plurality of transistors, represent the new multi-permutation.
18. The device as in claim 1 further comprising:
a memory comprising the plurality of transistors configured to store data values; and
a memory controller that is configured to store the data values in the memory by performing operations comprising:
a processor configured to perform operations of:
determining a sequential order of an initial analog level of a stored value in each cell of a plurality of cells in the device, wherein the sequential order is defined as a value x comprising
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19. The device as in claim 1 further comprising:
a memory comprising the plurality of transistors configured to store data values:
a memory controller that is configured to store the data values in the memory by performing operations comprising:
defining a predetermined rank configuration (d 1 , d 2 . . . d n ), wherein d i is the number of cells in the i th rank;
receiving a new multi-permutation defined by v=[v 1 , v 2 , . . . , v n ]∈S n that fits the predetermined rank configuration;
retaining analog levels of cells of a rank n in v;
programming cells of rank i in v for i=n−1, n−2, . . . , 1 such that analog levels of cells in a rank i are all higher than analog levels of cells of rank i+1 in v by at least a minimum rank differentiation.
20. The device as in claim 19 , wherein the analog level in each of the cells corresponds to a stored charge in a floating gate transistor.