IP Library Granted Patent US 9,208,276
Granted Patent B1
US 9,208,276 · App. 14/822,907 · Granted Dec 8, 2015

Method for generating layout pattern

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Quick Facts
Patent No.
US 9,208,276
App. No.
14/822,907
Granted
Dec 8, 2015
Kind
B1
Abstract

A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

Claims (14)

1. A method for generating a layout pattern comprising a FinFET structure layout, the method comprising:

providing a layout pattern to a computer system;

classifying the layout pattern into two sub-patterns and a blank pattern by the computer system, wherein the blank pattern is disposed between the two sub-patterns;

generating a plurality of first stripe patterns by the computer, wherein longitudinal edges of the first stripe patterns are aligned with longitudinal edges of the sub-patterns;

generating at least two second stripe patterns by the computer, wherein positions of the second stripe patterns corresponds to a position of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns; and

fabricating a photomask having the first stripe patterns and the second stripe patterns.

2. The method of claim 1 , wherein each of the sub-patterns comprises a plurality of stripe patterns.

3. The method of claim 1 , wherein a distance is defined between the two sub-patterns and a ratio of the distance to each of the pitches is not integral.

4. The method of claim 1 , wherein the first stripe patterns are respectively disposed at two sides of the second stripe patterns.

5. The method of claim 1 , wherein each of the first stripe patterns and the second stripe patterns respectively have long axes, and the long axes are parallel to one another.

6. The method according to claim 1 , wherein the first stripe patterns are grouped into at least two adjacent clusters, and a spacing between the adjacent clusters is less than 5 times a width of each of the first stripe patterns.

7. The method according to claim 6 , wherein the second stripe patterns are disposed between the clusters.

8. The method according to claim 1 , wherein the widths or the spacings of the second stripe patterns are equal to the widths or the spacings of the first stripe patterns.

9. The method according to claim 1 , further comprising performing an optical proximity correction to determine the widths and the spacings of the second stripe patterns.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2015
From: TSAO, PO-CHAO; HONG, SHIH-FANG; HUANG, CHIA-WEI; CHEN, MING-JUI; TZOU, SHIH-FANG; WEI, MING-TE
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036293/0809 →