Semiconductor device with a NAND circuit having four transistors
A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area.
1. A semiconductor device, comprising:
a NAND circuit including four transistors arranged in a line on a substrate, with a source, a drain, and a gate of each of the four transistors being hierarchically disposed in a direction perpendicular to the substrate, each of the four transistors having:
a silicon pillar with an upper portion and a lower portion;
an insulator surrounding a side surface of the silicon pillar;
a gate surrounding the insulator;
a source region disposed at the upper portion or the lower portion of the silicon pillar; and
a drain region disposed at the upper portion or the lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar,
the four transistors including:
a first p-channel MOS transistor,
a second p-channel MOS transistor,
a first n-channel MOS transistor, and
a second n-channel MOS transistor,
wherein:
the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to one another,
the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to one another,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of the first n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars,
the source region of the second n-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of first n-channel MOS transistor are connected to one another via a silicide region,
the source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to one another via a contact,
the source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a contact, and
the source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a silicide region.
2. The semiconductor device according to claim 1 , wherein the four transistors are arranged in a line in order of the first n-channel MOS transistor, the first p-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor.
3. The semiconductor device according to claim 1 , wherein the four transistors are arranged in a line in order of the second p-channel MOS transistor, the first p-channel MOS transistor, the first n-channel MOS transistor, and the second n-channel MOS transistor.
4. The semiconductor device according to claim 3 , wherein the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to each other via a contact.
5. The semiconductor device according to claim 1 , wherein the four transistors are arranged in a line in order of the first p-channel MOS transistor, the first n-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor.
6. A semiconductor device, comprising:
a NAND circuit including four transistors arranged in a line on a substrate, with a source, a drain, and a gate of each of the four transistors being hierarchically disposed in a direction perpendicular to the substrate, each of the four transistors having:
a silicon pillar with an upper portion and a lower portion;
an insulator surrounding a side surface of the silicon pillar;
a gate surrounding the insulator;
a source region disposed at the upper portion or the lower portion of the silicon pillar; and
a drain region disposed at the upper portion or the lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar,
the four transistors including:
a first p-channel MOS transistor,
a second p-channel MOS transistor,
a first n-channel MOS transistor, and
a second n-channel MOS transistor,
wherein:
the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to one another,
the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to one another,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, the drain region of the first n-channel MOS transistor, and the drain region of the second n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of the first n-channel MOS transistor are connected to one another via a silicide region,
the source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to one another via a contact and a silicide region,
the source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a contact, and
the source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a contact.
7. The semiconductor device according to claim 6 , wherein the four transistors are arranged in a line in order of the first n-channel MOS transistor, the first p-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor.
8. The semiconductor device according to claim 6 , wherein the four transistors are arranged in a line in order of the second p-channel MOS transistor, the first p-channel MOS transistor, the first n-channel MOS transistor, and the second n-channel MOS transistor.
9. The semiconductor device according to claim 8 , wherein the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to each other via a contact.
10. A semiconductor device, comprising:
a NAND circuit including four transistors arranged in a line on a substrate, with a source, a drain, and a gate of each of the four transistors being hierarchically disposed in a direction perpendicular to the substrate, each of the four transistors having:
a silicon pillar with an upper portion and a lower portion;
an insulator surrounding a side surface of the silicon pillar;
a gate surrounding the insulator;
a source region disposed at the upper portion or the lower portion of the silicon pillar; and
a drain region disposed at the upper portion or lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar,
the four transistors including
a first p-channel MOS transistor,
a second p-channel MOS transistor,
a first n-channel MOS transistor, and
a second n-channel MOS transistor,
wherein:
the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to one another,
the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to one another,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of the first n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars,
the source region of the second n-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of first n-channel MOS transistor are connected to one another via a silicide region,
the source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to one another via a contact and a silicide region,
the source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a contact,
the source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a contact, and
the four transistors are arranged in a line in order of the first p-channel MOS transistor, the first n-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor.
11. A semiconductor device, comprising:
a NAND circuit including four transistors arranged in a line on a substrate, with a source, a drain, and a gate of each of the four transistors being hierarchically disposed in a direction perpendicular to the substrate, each of the four transistors having:
a silicon pillar with an upper portion and a lower portion;
an insulator surrounding a side surface of the silicon pillar;
a gate surrounding the insulator;
a source region disposed at the upper portion or the lower portion of the silicon pillar; and
a drain region disposed at the upper portion or the lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar,
the four transistors including
a first p-channel MOS transistor,
a second p-channel MOS transistor,
a first n-channel MOS transistor, and
a second n-channel MOS transistor,
wherein:
the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to one another,
the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to one another, the source region of the first p-channel MOS transistor, the source region of
the second p-channel MOS transistor, and the source region of the first n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars,
the drain region of the second n-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar,
the drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of first n-channel MOS transistor are connected to one another via a contact,
the source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to one another via a silicide region,
the source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a silicide region, and
the source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a contact.
12. The semiconductor device according to claim 11 , wherein the four transistors are arranged in a line in order of the first p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor, and the second p-channel MOS transistor.
13. The semiconductor device according to claim 12 , wherein the source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to the power supply terminal via a silicide region and a contact, the silicide region extending in a direction perpendicular to a direction in which the four transistors are arranged in a line.
14. The semiconductor device according to claim 13 , wherein the NAND circuit is one of a plurality of NAND circuits that are arranged in a direction perpendicular to the direction in which the four transistors are arranged in a line, the extended silicide regions are connected to one another, and one of the plurality of NAND circuits is connected to the power supply terminal via the extended silicide regions and a contact.
15. The semiconductor device according to claim 11 , wherein the four transistors are arranged in a line in order of the second p-channel MOS transistor, the first p-channel MOS transistor, the first n-channel MOS transistor, and the second n-channel MOS transistor.
16. The semiconductor device according to claim 15 , wherein a gate line of the second p-channel MOS transistor and a gate line of the second n-channel MOS transistor are supplied with signals through different signal lines via contacts.