Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
View Patent ↗Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
1. A method of forming a semiconductor die assembly, the method comprising:
electrically coupling a plurality of first semiconductor dies together in a single stack;
electrically coupling the single stack of first semiconductor dies to a second semiconductor die such that the stack of first semiconductor dies is centered with respect to the second semiconductor die along at least one axis, the second semiconductor die having a peripheral portion that extends laterally outward beyond at least one side of the stack of first semiconductor dies, and wherein the stack of first semiconductor dies forms a first thermal path that transfers heat away from the second semiconductor die;
depositing an underfill material between the first semiconductor dies, wherein the underfill material extends from between the first semiconductor dies onto the peripheral portion of the second semiconductor die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the second semiconductor die adjacent to at most a first side and a second side of the single stack of first semiconductor dies and spaced laterally apart from the at most first and second sides of the single stack of first semiconductor dies, wherein the thermal transfer feature is a blank silicon member, and wherein the thermal transfer feature forms a second thermal path away from the second semiconductor die that is separate from the first thermal path; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation generally corresponding to that of a topmost one of the first semiconductor dies in the stack of first semiconductor dies, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation generally corresponding to that of the topmost one of the first semiconductor dies.
2. The method of claim 1 wherein:
the first semiconductor dies are memory dies; and
electrically coupling the stack of first semiconductor dies to the second semiconductor die comprises electrically coupling the stack of memory dies to a logic die.
3. The method of claim 1 wherein disposing the thermally conductive casing includes disposing the thermally conductive casing around at least a portion of the first and second semiconductor dies, and wherein the thermally conductive casing includes a cavity configured to receive at least a portion of the first and second semiconductor dies.
4. The method of claim 1 , further comprising:
electrically coupling the second semiconductor die to a package substrate; and
thermally contacting a base portion of the thermally conductive casing with the package substrate.
5. The method of claim 1 wherein the thermal transfer feature is a first thermal transfer feature, and wherein the method further comprises superimposing a second thermal transfer feature with the first semiconductor dies.
6. The method of claim 5 wherein superimposing the second thermal transfer feature with the first semiconductor dies comprises positioning an upper surface of the second thermal transfer feature to be generally coplanar with an upper surface of the first thermal transfer feature, and wherein the method further comprises thermally contacting the thermally conductive casing with the upper surface of the second thermal transfer feature.
7. The method of claim 5 wherein the second thermal transfer feature is a blank silicon member.
8. The method of claim 1 , further comprising forming a plurality of thermally conductive elements extending between the first and second semiconductor dies, wherein the thermally conductive elements are electrically isolated from the first and second semiconductor dies.
9. A method of forming a semiconductor die assembly, the method comprising:
electrically coupling a plurality of memory dies together in a single stack;
electrically coupling the single stack of memory dies to a logic die such that the stack of memory dies is centered with respect to the logic die along at least one axis, wherein the logic die includes a peripheral portion extending laterally outward beyond at least one side of the memory dies;
depositing an underfill material between the memory dies, wherein the underfill material extends from between the memory dies onto the peripheral portion of the logic die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the logic die adjacent to at most a first side and a second side of the single stack of memory dies and spaced laterally apart from the at most first and second sides of the stack of memory dies, wherein the thermal transfer feature is a blank silicon member, wherein the memory dies and the thermal transfer feature provide separate thermal paths that transfer heat away from the logic die; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation proximate that of the memory die spaced farthest from the logic die, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation proximate that of the memory die spaced farthest from the logic die.
10. The method of claim 9 wherein electrically coupling the plurality of memory dies together in a single stack comprises electrically coupling at least eight memory dies together.
11. The method of claim 9 wherein the thermally conductive casing has a cavity that is shaped to receive the memory dies and the logic die, and wherein the thermally conductive casing comprises a metal.
12. The method of claim 9 wherein the thermally conductive casing thermally contacts the memory die spaced farthest from the logic die.
13. The method of claim 9 wherein the thermally conductive casing thermally contacts the memory dies to define a first thermal path and thermally contacts the thermal transfer feature to define a second thermal path spaced laterally apart from the memory dies.
14. The method of claim 9 , further comprising forming a plurality of thermally conductive elements extending between the memory dies and between the logic die and the lowermost memory die, wherein the thermally conductive elements are electrically isolated from the memory and logic dies.
15. The method of claim 9 wherein the thermal transfer feature is a first thermal transfer feature, and wherein the method further comprises superimposing a second thermal transfer feature with the memory dies, wherein the first and second thermal transfer features are pre-formed blank silicon members.
16. The method of claim 15 wherein superimposing the second thermal transfer feature with the memory dies comprises positioning an upper surface of the second thermal transfer feature to be generally coplanar with an upper surface of the first thermal transfer feature, and wherein the method further comprises thermally contacting the thermally conductive casing with the upper surface of the second thermal transfer feature.