Method of fabricating semiconductor structure
View Patent ↗The present invention provides a method for improving gate coupling ratio of a flash memory device and a protruding floating gate is formed. First, a substrate having a plurality of isolation structures is formed. Then, a first conductive layer is formed overlaying the substrate. A chemical-mechanical polishing process is performed to planarize the first conductive layer. After that, a portion of the isolation structures is removed, and a second conductive layer is formed overlaying the first conductive layer and the isolation structures. Finally, a lithography process with a photomask can be used to define a mask that covers the first conductive layer and the second conductive layer, and then an insulating layer is deposited overlaying the substrate, so that a third conductive layer is formed overlaying the insulating layer.
1. A method for fabricating a semiconductor structure, comprising the steps of:
forming a plurality of isolation structures in the substrate;
forming a first conductive layer overlaying the substrate;
performing a chemical-mechanical polishing process to planarize the first conductive layer;
removing a portion of the isolation structures;
forming a second conductive layer overlaying the first conductive layer and the isolation structures;
patterning the first conductive layer and the second conductive layer;
forming an insulating layer overlaying the substrate; and
forming a third conductive layer overlaying the insulating layer.
2. The method according to claim 1 , wherein the isolation structures are shallow trench isolation (STI) structures.
3. The method according to claim 1 , wherein the step of forming a first conductive layer overlaying the substrate further comprises a process of performing a physical vapor deposition (PVD) or a chemical vapor deposition process (CVD).
4. The method according to claim 1 , wherein the step of removing the portion of the isolation structures further comprises a process of performing a wet etching or a dry etching.
5. The method according to claim 1 , wherein the first conductive layer is made of a doped polysilicon layer.
6. The method according to claim 1 , wherein the second conductive layer is made of a doped polysilicon layer.
7. The method according to claim 1 , wherein the step of patterning the second conductive layer further comprises etching and lithography processes.
8. The method according to claim 1 , wherein the insulating layer is an inter-poly dielectric layer.
9. The method according to claim 1 , wherein the first conductive layer and the second conductive layer are collectively formed a floating gate.
10. The method according to claim 1 , wherein the third conductive layer is made of a doped polysilicon layer.
11. The method according to claim 1 , wherein the third conductive layer is a control gate.
12. The method according to claim 1 , wherein the step of removing the portion of the isolation structures further comprises a process of forming a remained isolation structure having an upper surface lowered than an upper surface of the first conductive layer.
13. The method according to claim 12 , wherein the isolation structures comprise insulating materials.
14. The method according to claim 13 , wherein the insulating materials are selected from the group consisting of boro phosphosilicate glass (BPSG), phosophosilicate glass (PSG), CVD oxide, fluorinated glass (FSG) or the like.