IP Library Granted Patent US 9,761,599
Granted Patent B2
US 9,761,599 · App. 14/827,695 · Granted Sep 12, 2017

Integrated structures containing vertically-stacked memory cells

Inventors: Haitao Liu (Boise, ID); Chandra Mouli (Boise, ID); Sergei Koveshnikov (Boise, ID); Dimitrios Pavlopoulos (Boise, ID); Guangyu Gavin Huang (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11556H01L21/28273H01L21/28282H01L27/11582
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Quick Facts
Patent No.
US 9,761,599
App. No.
14/827,695
Granted
Sep 12, 2017
Kind
B2
Abstract

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Claims (43)

1. An integrated structure comprising:

a stack of alternating dielectric levels comprising dielectric material and conductive levels comprising conductive material, the conductive material having upper and lower surfaces in direct contact with the dielectric material of the dielectric levels;

vertically-stacked memory cells within the conductive levels, each of the memory cells comprising a charge storage material, a charge blocking material and a gate dielectric material; the conductive material, the charge storage material, the gate dielectric and the charge blocking material having coplanar upper surfaces in direct contact with dielectric material comprised by the dielectric levels;

an opening extending through the stack, the opening having opposing vertical sidewalls along the stack; and

a germanium-comprising channel material within the opening and along the memory cells, the germanium-comprising channel material entirely filling the opening and being in direct contact with the opposing vertical sidewalls.

2. The integrated structure of claim 1 wherein an entirety of the germanium-comprising channel material comprises Si (1-x) Ge x ; where x is a number greater than zero, and less than or equal to 1.

3. The integrated structure of claim 1 wherein at least some of the germanium-comprising channel material comprises a concentration of germanium within a range of from about 10 atomic percent to about 30 atomic percent.

4. The integrated structure of claim 1 wherein the germanium-comprising channel material comprises a horizontally-extending gradient of germanium concentration.

5. The integrated structure of claim 4 wherein the germanium-comprising channel material has an exterior surface along a sidewall of the opening and an interior region horizontally offset from the exterior surface, and wherein the germanium concentration increases along a direction from the exterior surface toward the interior region.

6. The integrated structure of claim 4 wherein the germanium-comprising channel material has an exterior surface along a sidewall of the opening and an interior region horizontally offset from the exterior surface, and wherein the germanium concentration decreases along a direction from the exterior surface toward the interior region.

7. The integrated structure of claim 1 further comprising at least one dopant within the germanium-comprising channel material; the dopant being p-type, n-type or i-type.

8. The integrated structure of claim 7 wherein the germanium-comprising channel material comprises a horizontally-extending gradient of dopant concentration.

9. The integrated structure of claim 7 wherein the germanium-comprising channel material comprises a horizontally-extending gradient of dopant concentration and a horizontally-extending gradient of germanium concentration.

10. An integrated structure comprising, along a cross-section:

a stack of alternating dielectric levels and conductive levels, the conductive levels comprising a conductive material that directly contacts dielectric material comprised by the adjacent dielectric levels;

vertically-stacked memory cells within the conductive levels, each of the memory cells comprising a charge storage material, a charge blocking material and a gate dielectric material; the conductive material, the charge storage material, the gate dielectric and the charge blocking material having coplanar upper surfaces in direct contact with dielectric material comprised by the dielectric levels;

an opening extending through the stack, the opening having opposing vertical sidewalls along the stack;

germanium-containing channel material liners within the opening and along the memory cells, the germanium-containing channel material liners being in direct contact with the opposing vertical sidewalls; and

an insulator-filled hollow within the opening and between the germanium-containing liners.

11. The integrated structure of claim 10 wherein the germanium-containing channel material liners comprise horizontally-extending gradients of germanium concentration.

12. The integrated structure of claim 11 wherein the germanium-containing channel material liners have exterior surfaces along sidewalls of the opening and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each liner increases along a direction from the exterior surface toward the interior region.

13. The integrated structure of claim 11 wherein the germanium-containing channel material liners have exterior surfaces along sidewalls of the opening and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each liner decreases along a direction from the exterior surface toward the interior region.

14. The integrated structure of claim 11 wherein the germanium-containing channel material liners have first exterior surfaces along sidewalls of the opening, second exterior surfaces along the insulator-filled hollow, and interior regions between the first and second exterior surfaces; and wherein the germanium concentration of each liner increases along a first direction from the first exterior surface toward the interior region, and increases along a second direction from the second exterior surface toward the interior region.

15. An integrated structure comprising, along a cross-section:

a stack of alternating dielectric levels and conductive levels, the conductive levels comprising a conductive material that directly contacts dielectric material comprised by the adjacent dielectric levels;

vertically-stacked memory cells within the conductive levels, each of the memory cells comprising a charge storage material, a charge blocking material and a gate dielectric material; the conductive material, the charge storage material, the gate dielectric and the charge blocking material having coplanar upper surfaces in direct contact with dielectric material comprised by the dielectric levels;

an opening extending through the stack, the opening having opposing vertical sidewalls along the stack;

non-germanium-containing channel material liners in direct contact with the sidewalls of the opening and along the memory cells, the non-germanium-containing channel material consisting of one or more semiconductor materials selected from the group consisting of silicon, doped silicon, III/V semiconductor material, doped III/V semiconductor material, II/VI semiconductor material and doped II/VI material;

germanium-containing channel material liners within the opening and along the non-germanium-containing material liners; and

an insulator-filled hollow within the opening and between the germanium-containing liners.

16. The integrated structure of claim 15 wherein the germanium-containing channel material liners comprise horizontally-extending gradients of germanium concentration.

17. The integrated structure of claim 16 wherein the germanium-containing channel material liners have exterior surfaces along the non-germanium-containing channel material liners and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each germanium-containing channel material liner increases along a direction from the exterior surface toward the interior region.

18. The integrated structure of claim 16 wherein the germanium-containing channel material liners have exterior surfaces along the non-germanium-containing channel material liners and interior regions horizontally offset from the exterior surfaces, and wherein the germanium concentration of each germanium-containing channel material liner decreases along a direction from the exterior surface toward the interior region.

19. The integrated structure of claim 16 wherein the germanium-containing channel material liners have first exterior surfaces along the non-germanium-containing channel material liners, second exterior surfaces along the insulator-filled hollow, and interior regions between the first and second exterior surfaces; and wherein the germanium concentration of each germanium-containing channel material liner increases along a first direction from the first exterior surface toward the interior region, and increases along a second direction from the second exterior surface toward the interior region.

20. The integrated structure of claim 15 wherein the non-germanium-containing channel material liners comprise silicon-containing semiconductor material.

21. The integrated structure of claim 20 wherein the semiconductor material comprises one or more of monocrystalline silicon, amorphous silicon and polycrystalline silicon.

22. An integrated structure comprising, along a cross-section:

a stack of alternating dielectric levels and conductive levels;

vertically-stacked memory cells within the conductive levels;

an opening extending through the stack, the opening having opposing vertical sidewalls along the stack;

non-germanium-containing channel material liners in direct contact with the sidewalls of the opening and along the memory cells, the non-germanium-containing channel material consisting of one or more semiconductor materials comprising III/V semiconductor material or II/VI semiconductor material;

germanium-containing channel material liners within the opening and along the non-germanium-containing material liners; and

an insulator-filled hollow within the opening and between the germanium-containing liners.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2015
From: LIU, HAITAO; MOULI, CHANDRA; KOVESHNIKOV, SERGEI; PAVLOPOULOS, DIMITRIOS; HUANG, GUANGYU
To: MICRON TECHNOLOGY, INC.
Reel/Frame 036339/0312 →
Continuity (1)
Related Publication 20170053986A1 · Feb 23, 2017