Threshold voltage adjustment of a transistor
View Patent ↗A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.
1. A transistor, comprising:
a channel extending laterally between a source and a drain within a substrate; and
a gate disposed laterally over the channel, wherein the channel includes at least one discrete doped region between the source and the drain, wherein the drain, the source, and the at least one discrete doped region are of a same substrate conductivity type, and are separated from each other by a region of the channel that is of a different substrate conductivity type.
2. The transistor of claim 1 , further comprising double diffused implant regions disposed adjacent each of the source and the drain.
3. The transistor of claim 1 , further comprising double diffused implant regions disposed adjacent the at least one discrete doped region.
4. The transistor of claim 1 , wherein each of the source and the drain includes:
a main portion; and
a lightly doped extension that is adjacently located inward from the main portion, and that extends under at least a portion of the gate.
5. The transistor of claim 4 , wherein the at least one discrete doped region is located in the channel between the lightly doped extensions of the source and the drain.
6. The transistor of claim 5 , wherein the at least one discrete doped region includes a plurality of discrete doped regions that are located in the channel between the lightly doped extensions of the source and the drain.
7. The transistor of claim 6 , wherein further comprising:
double diffused implant regions disposed adjacent each of the source and the drain;
double diffused implant regions disposed adjacent each discrete doped region of the plurality of discrete doped regions; and
enhancement implant regions that extend in the channel between neighboring double diffused implant regions of the source, the discrete doped regions, and the drain.
8. The transistor of claim 7 , wherein the each of the double diffused implant regions are more heavily doped than the enhancement implants, and wherein each of the source and the drain are more heavily doped than the double implant diffused regions.
9. The transistor of claim 6 , wherein the plurality of discrete doped regions are disposed in the channel in a two-dimensional pattern along a length and width of the channel between the source and the drain of the same transistor.
10. The transistor of claim 1 , wherein the gate includes at least one aperture over the at least one discrete doped region.
11. A method of forming a transistor, the method comprising:
forming a channel extending laterally between a source and a drain within a substrate;
forming at least one discrete doped region within the channel;
forming a source and a drain on opposing ends of the channel, wherein the drain, the source, and the at least one discrete doped region are of a same substrate conductivity type, and are separated from each other by a region of the channel that is of a different substrate conductivity type; and
forming a gate laterally over the channel.
12. The method of claim 11 , wherein forming the gate laterally over the channel includes forming at least one aperture in the gate above the channel.
13. The method of claim 12 , wherein forming the at least one discrete doped region includes implanting the at least one discrete doped region in the channel through the at least one aperture in the gate.
14. The method of claim 13 , further comprising implanting a double-diffused structure adjacent the at least one discrete doped region through the at least one implant aperture of the gate.
15. The method of claim 13 , wherein forming the at least one discrete doped region includes implanting a plurality of discrete doped regions in the channel through the corresponding apertures in the gate.
16. The method of claim 12 , wherein forming the channel comprises:
disposing a masking material on a substrate, the masking material having an opening therethrough to the substrate; and
applying an enhancement implant to the channel defined by the opening through the masking material.
17. The method of claim 16 , wherein forming the gate laterally over the channel comprises:
disposing a gate insulation material over the channel;
disposing a gate material over the gate insulation material; and
forming at least one aperture through the gate material and the gate insulation material to the channel.
18. The method of claim 17 , further comprising applying an implantation using the gate as a mask to simultaneously form:
lightly doped structures in the substrate through the at least one aperture to form at least a portion of the at least one discrete doped region; and
lightly doped structures in the substrate on opposing ends of the gate.
19. The method of claim 18 , further comprising applying an angular implantation using the gate as a mask to simultaneously form:
double diffused doped structures in the substrate through the at least one aperture around the portion of the at least one discrete doped region; and
double diffused doped structures in the substrate on opposing ends of the gate.
20. The method of claim 19 , further comprising applying a high concentration implantation in the substrate on the opposing ends of the gate to form the source and the drain surrounded by the double diffused doped structures on the opposing ends of the channel.