Integrated mixed-signal ASIC with ADC, DAC, and DSP

1. An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry, comprising:

a plurality of radiation tolerant high speed analog to digital conversion (ADC) units, each configured to take in an RF signal and output a sampled digital signal;

a plurality of radiation tolerant high speed digital to analog conversion (DAC) units, each configured to take in a sampled digital signal and output an RF signal;

a plurality of radiation tolerant digital inputs;

a plurality of radiation tolerant digital outputs;

a plurality of radiation tolerant digital signal processing (DSP) cores, each capable of processing data from one high speed ADC unit and outputting the processed data on one or more digital outputs; and

a plurality of radiation tolerant digital signal processing (DSP) cores, each capable of processing data from a digital input and outputting the processed data to one DAC unit.

2. The integrated ADDA RF transceiver for satellite applications according to claim 1 , further including selectively providing the output from a single high speed ADC unit to one or more DSP cores.

3. The integrated ADDA RF transceiver for satellite applications according to claim 1 , further including providing the output from one or more DSP cores to a single high speed DAC unit.

4. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein each of the DSP cores include:

a digital mixer operative to perform frequency translation of data from RF to baseband or from baseband to RF;

a decimating filter operative to suppress aliasing and downsample a frequency downconverted baseband signal to its information bandwidth, to reduce an output data rate; and

an interpolating filter operative to suppress images while upsampling a baseband signal to an output sample rate prior to frequency upconversion, to reduce an input sample rate.

5. The integrated ADDA RF transceiver for satellite applications according to claim 4 , each of the DSP cores further including a digital frequency synthesizer, wherein the digital frequency synthesizer comprises:

a lookup table (LUT) storing a sampled sinusoid, wherein the LUT includes a plurality of lookup table addresses with a sample value for each address; and

a digital phase accumulator, wherein phase is encoded as an integer value mapping to one of the lookup table addresses;

wherein the digital phase accumulator is incremented, and a sample is produced from the LUT at the mapped lookup table address.

6. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein said DSP core includes:

a cascade of decimating frequency translating filters, to hierarchically downconvert and downsample digital data from one of the high-speed ADC units; and

a cascade of interpolating frequency translating filters, to hierarchically upconvert and upsample digital data to feed one of the high-speed DAC units.

7. The integrated ADDA RF transceiver for satellite applications according to claim 4 , further comprising a digital tune frequency input for rapidly changing a frequency of the data during operation of the ADDA unit.

8. The integrated ADDA RF transceiver for satellite applications according to claim 1 , further comprising a digital bandwidth selection input for rapidly changing a processing bandwidth, which corresponds to an interpolation or decimation ratio.

9. The integrated ADDA RF transceiver for satellite applications according to claim 1 , further comprising a TDMA time slot power activation-deactivation time synchronization input, to save power when operating during an inactive portion of a TDMA frame.

10. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein the digital inputs and outputs include a configurable complex floating point data converter to conserve digital data input and output communication bandwidth while preserving data fidelity regardless of an interpolation or decimation ratio.

11. The integrated ADDA RF transceiver for satellite applications according to claim 10 , wherein the configurable complex floating point data converter receives complex numbers that include i and q portions that share one or more bits related to exponents thereof.

12. The integrated ADDA RF transceiver for satellite applications according to claim 1 , further comprising radiation hardened flip flops in place of configuration and other registers to ensure operation in a space environment with a low error rate.

13. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein the transceiver is implemented on a single monolithic silicon device.

14. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein the transceiver is implemented on an ASIC.

15. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein the transceiver is implemented on a multi-chip module.

16. The integrated ADDA RF transceiver for satellite applications according to claim 1 , wherein the transceiver is implemented on a hybrid device including active and passive integrated circuit elements.

17. The integrated ADDA RF transceiver according to claim 1 , further including selectively disabling unused digital inputs or outputs when processing less than a maximum bandwidth of the integrated ADDA RF transceiver.

18. The integrated ADDA RF transceiver according to claim 1 , further including utilizing flexible data packing of data in the digital outputs and flexible data unpacking of data from the digital inputs.

19. A method used in a satellite, comprising:

providing an Application Specific Integrated Circuit (ASIC) that:

down-converts a first RF signal and converts it to a lower frequency signal;

receives the lower frequency signal and converts it to a first digital signal;

converts the first digital signal to a second digital signal;

receives the second digital signal and converts it to an analog signal; and

receives the analog signal and converts it to a second RF signal.

20. A method used in a satellite, comprising:

providing an Application Specific Integrated Circuit (ASIC) that:

down-converts a first RF signal and converts it to a lower frequency signal;

receives the lower frequency signal and converts it to a first digital signal;

receives a second digital signal and converts it to an analog signal; and

receives the analog signal and converts it to a second RF signal.

21. A method used in a satellite, comprising:

providing an Application Specific Integrated Circuit (ASIC) that:

receives a first analog RF signal and converts it to a first digital signal;

down-converts the first digital signal to create a lower-frequency second digital signal;

receives a third digital signal and up-converts the third digital signal to create a higher-frequency fourth digital signal; and

converts the fourth digital signal to a second analog RF signal.

22. An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry, comprising:

a plurality of high speed analog to digital conversion (ADC) units, each configured to take in an RF signal and output a sampled digital signal;

a plurality of high speed digital to analog conversion (DAC) units, each configured to take in a sampled digital signal and output an RF signal;

a plurality of digital inputs;

a plurality of digital outputs; and

a plurality of digital signal processing (DSP) cores, each capable of processing data from one high speed ADC unit and outputting the processed data on one or more digital outputs and capable of processing data from a digital input and outputting the processed data to one DAC unit;

wherein the entire ADDA RF transceiver is contained in a single package;

wherein the circuitry described above has been designed to be radiation tolerant;

wherein the circuitry described above can handle a broad range of RF frequencies and bandwidths.