Semiconductor device and operating method thereof
View Patent ↗A semiconductor device includes a main processor, a normally-off processor, and at least one oxide semiconductor random access memory (RAM). The normally-off processor includes at least one oxide semiconductor transistor. The main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor. The oxide semiconductor RAM is connected to the normally-off processor. An operating method of the semiconductor includes backing up data from the main processor to the normally-off processor and/or the oxide semiconductor RAM.
1. A semiconductor device, comprising:
a main processor;
a normally-off processor comprising at least one oxide semiconductor transistor, wherein the main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor; and
at least one oxide semiconductor random access memory (RAM) connected to the normally-off processor, wherein the normally-off processor and the oxide semiconductor RAM are integrated in one die, and the oxide semiconductor RAM comprises a dynamic random access memory (DRAM) shared by the main processor and the normally-off processor, wherein the main processor and the normally-off processor are disposed on different dies.
2. The semiconductor device of claim 1 , wherein the oxide semiconductor transistor comprises an indium gallium zinc oxide (IGZO) transistor, and the oxide semiconductor RAM comprises an IGZO RAM.
3. The semiconductor device of claim 1 , further comprising:
a peripheral unit connected to the main processor and the normally-off processor, wherein the peripheral unit comprises a global positioning system (GPS) unit, a wireless networking unit, or a sensor unit.
4. The semiconductor device of claim 1 , wherein the main processor is a silicon semiconductor processor.
5. An operating method of a semiconductor device, comprising:
providing the semiconductor device of claim 1 ; and
backing up data from the main processor to the normally-off processor and/or the oxide semiconductor RAM.
6. The operating method of claim 5 , wherein the semiconductor device further comprises a peripheral unit connected to the main processor and the normally-off processor, and the operating method of the semiconductor device further comprises:
collecting data from the peripheral unit to the normally-off processor and/or updating a running program by the normally-off processor when the main processor enters a sleep mode.
7. The operating method of claim 6 , wherein the normally-off processor and the oxide semiconductor RAM are integrated in one die, the semiconductor device further comprises a high speed RAM connected to the main processor and the die of the normally-off processor and the oxide semiconductor RAM, and the operating method of the semiconductor device further comprises:
backing up data from the main processor to the normally-off processor and/or the oxide semiconductor RAM before and after the sleep mode.