Device with heteroepitaxial structure made using a growth mask
A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
1. A device comprising:
a semiconductor substrate comprising single crystal silicon;
a seed area delineated with a selective growth mask on the semiconductor substrate, the seed area comprising a first material and having a linear surface dimension of less than 100 nm;
a heteroepitaxial layer grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material, a source region and a drain region; and
a gate, a source electrode and a drain electrode positioned on the heteroepitaxial layer to form a FinFET,
wherein the seed area comprises Si (001) and the heteroepitaxial layer comprises a material chosen from a Group III-N semiconductor material, wherein the heteroepitaxial layer forms the fin of the FinFET, and further wherein there are substantially zero threading dislocation defects in the heteroepitaxial layer.
2. The device of claim 1 , wherein the linear surface dimension is less than 25 nm.
3. The device of claim 1 , wherein the seed area is raised from the semiconductor substrate surface to form a pedestal.
4. The device of claim 1 , wherein the seed area is formed planar with the surface of the semiconductor substrate.
5. A device comprising:
a semiconductor substrate;
a seed area delineated with a selective growth mask on the semiconductor substrate, the seed area comprising a first material and having a linear surface dimension of less than 100 nm; and
a heteroepitaxial layer grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material,
wherein the heteroepitaxial layer is a vertical nanowire, the vertical nanowire being doped to provide a source region, a drain region and a gate region, the device forming a vertical transistor.