Fabrication of III-Nitride Power Semiconductor Device
A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.
1 - 62 . (canceled)
63 : A method of fabricating a power semiconductor device, comprising:
providing a substrate;
growing a first III-nitride layer using a growth method selected from the group consisting of MBE and HVPE, and a second III-nitride layer over said first III-nitride layer using a MOCVD growth method;
forming an active semiconductor region, wherein at least one of said first and second III-nitride layers act to transition lattice mismatch between said substrate and said active semiconductor region.
64 : The method of claim 63 , wherein at least one of said first and second III-nitride layers further acts to transition thermal expansion characteristics between said substrate and said active semiconductor region.
65 : The method of claim 63 , wherein said active semiconductor region comprises first and second III-nitride semiconductor bodies.
66 : The method of claim 63 , wherein said substrate comprises material selected from the group consisting of silicon, silicon carbide, and sapphire.
67 : The method of claim 63 , wherein said first III-nitride layer has a uniform composition.
68 : The method of claim 63 , wherein said first III-nitride layer has a graded composition.
69 : The method of claim 63 , wherein said second III-nitride layer has a uniform composition.
70 : The method of claim 63 , wherein said second III-nitride layer has a graded composition.
71 : A method of fabricating a power semiconductor device, comprising:
providing a substrate;
growing a first III-nitride layer using a MOCVD growth method, and a second III-nitride layer over said first III-nitride layer using a growth method selected from the group consisting of HVPE and MBE;
forming an active semiconductor region, wherein at least one of said first and second III-nitride layers act to transition lattice mismatch between said substrate and said active semiconductor region.
72 : The method of claim 71 , wherein at least one of said first and second III-nitride layers further acts to transition thermal expansion characteristics between said substrate and said active semiconductor region.
73 : The method of claim 71 , wherein said active semiconductor region comprises first and second III-nitride semiconductor bodies.
74 : The method of claim 71 , wherein said substrate comprises material selected from the group consisting of silicon, silicon carbide, and sapphire.
75 : The method of claim 71 , wherein said first III-nitride layer has a uniform composition.
76 : The method of claim 71 , wherein said first III-nitride layer has a graded composition.
77 : The method of claim 71 , wherein said second III-nitride layer has a uniform composition.
78 : The method of claim 71 , wherein said second III-nitride layer has a graded composition.