IP Library › Granted Patent US 9,653,535
Granted Patent B2
US 9,653,535 · App. 14/831,487 · Granted May 16, 2017

DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods

Inventors: Nicolas L. Breil (Wappingers Falls, NY); Ricardo A. Donaton (Cortlandt Manor, NY); Dong Hun Kang (Hopewell Junction, NY); Herbert L. Ho (New Windsor, NY); Rishikesh Krishnan (Painted Post, NY)
Assignee: International Business Machines Corporation
H01L28/91H01L21/283H01L27/1082H01L27/1087H01L27/10832H01L27/10858H01L27/10867H01L28/90
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Quick Facts
Patent No.
US 9,653,535
App. No.
14/831,487
Granted
May 16, 2017
Kind
B2
Abstract

Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

Claims (20)

1. A method of forming a deep trench capacitor, the method comprising:

forming a deep trench in a substrate;

forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench,

wherein the co-depositing of the refractory metal and the silicon includes alternately depositing the refractory metal and the silicon into the deep trench; and

filling a remaining portion of the deep trench with a semiconductor.

2. The method of claim 1 , further comprising, prior to forming the MIM stack:

enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; and

epitaxially forming a compressive stress layer in the lower portion of the deep trench.

3. The method of claim 2 , wherein the enlarging includes depositing an etch resistant layer over an upper portion of the deep trench, and performing a wet etch of the lower portion of the deep trench.

4. The method of claim 2 , wherein the compressive stress layer forming includes epitaxially growing silicon germanium on a surface of the lower portion of the deep trench.

5. The method of claim 4 , further comprising doping the silicon germanium with an n-type dopant.

6. The method of claim 1 , wherein the MIM stack forming further includes forming a node dielectric layer and an inner electrode layer over the outer electrode.

7. A method of forming a deep trench capacitor, the method comprising:

forming a deep trench in a substrate;

enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench;

epitaxially forming a compressive stress layer only in the lower portion of the deep trench directly against the substrate;

forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench;

wherein the co-depositing of the refractory metal and the silicon includes alternately depositing the refractory metal and the silicon into the deep trench; and

filling a remaining portion of the deep trench with a semiconductor.

8. The method of claim 7 , wherein the co-depositing of the refractory metal and the silicon includes alternately depositing the refractory metal and the silicon into the deep trench.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2015
From: BREIL, NICOLAS L.; DONATON, RICARDO A.; KANG, DONG HUN; HO, HERBERT L.; KRISHNAN, RISHIKESH
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036390/0417 →
Continuity (2)
Division 14242092 · Apr 1, 2014
Related Publication 20150357402A1 · Dec 10, 2015