Processor-in-memory-and-storage architecture

1. An apparatus comprising:

a memory;

a processor core in communication with the memory, wherein the processor core comprises a plurality of sub-cores in which a numeric range of each of the plurality of sub-cores is less than a total numeric range of the processor core; and

a code analyzer in communication with the memory and the plurality of sub-cores of the processor core, wherein the code analyzer performs error mitigation using code words received from the plurality of sub-cores.

2. The apparatus of claim 1 , wherein the code analyzer performs data error detection using a plurality of residues received from the plurality of sub-cores in which the plurality of residues represent a code word.

3. The apparatus of claim 2 , wherein each sub-core of the plurality of sub-cores comprises:

a datapath; and

a control unit.

4. The apparatus of claim 3 , wherein the datapath comprises:

a set of arithmetic logic units that outputs a residue based on the code word and modular arithmetic, wherein the set of arithmetic logic units is associated with a unique modulus.

5. The apparatus of claim 3 , wherein the sub-core further comprises:

a cache.

6. The apparatus of claim 1 , wherein each sub-core of the plurality of sub-cores executes a same sequence of instructions.

7. The apparatus of claim 6 , wherein the code analyzer analyzes a plurality of residues that represent a code word to control execution of conditional branches by the plurality of sub-cores.

8. The apparatus of claim 1 , wherein the code analyzer performs memory address validation for the processor core using the code words.

9. The apparatus of claim 1 , wherein the memory comprises:

an adiabatic memory circuit in communication with the plurality of sub-cores of the processor core.

10. The apparatus of claim 9 , wherein the adiabatic memory circuit comprises:

a memory array;

a switch that electrically connects to one row of the memory array per cycle; and

an energy storage unit that is electrically connected to the memory array through the switch.

11. The apparatus of claim 10 , wherein the energy storage unit recycles energy from the memory array to reduce heat loss.

12. The apparatus of claim 11 , wherein the energy storage unit comprises:

an inductor.

13. The apparatus of claim 1 , wherein the numeric range is a number of different numerical values that can be represented by a sub-core and the total numeric range is a number of different numerical values that can be represented by the processor core.

14. A computing system comprising:

a processor comprised of a set of processor cores, wherein a processor core in the set of processor cores comprises:

a plurality of sub-cores in which a numeric range of each of the plurality of sub-cores is less than a total numeric range of the processor core;

a memory in communication with the processor; and

a code analysis system in communication with the processor and the memory, wherein the code analysis system comprises:

a set of code analyzers in communication with the set of processor cores, wherein each code analyzer performs data error detection for data processed by a corresponding processor core of the set of processor cores and performs memory address validation for the corresponding processor core.

15. The computing system of claim 14 , wherein the memory comprises:

a plurality of memory arrays, wherein a single processor core of the set of processor cores connects to a particular memory array of the plurality of memory arrays at a time.

16. The computing system of claim 14 , wherein the memory comprises:

an adiabatic memory circuit that includes an energy storage unit.

17. The computing system of claim 14 , wherein the numeric range is a number of different numerical values that can be represented by a sub-core and the total numeric range is a number of different numerical values that can be represented by the processor core.

18. A method for performing reliable general-purpose computing, the method comprising:

processing, by each sub-core of a plurality of sub-cores of a processor core, a same instruction at a same time;

receiving, by a code analyzer, a plurality of residues that represent a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores;

determining, by the code analyzer, whether the plurality of residues are consistent or inconsistent; and

performing, by the code analyzer and the plurality of sub-cores, a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

19. The method of claim 18 , wherein performing the set of operations comprises:

sending, by the code analyzer, an inconsistent result to the plurality of sub-cores in response to a determination that the plurality of residues are inconsistent regardless of whether the code word is the memory address code or the data code.

20. The method claim 19 further comprising:

correcting, by the plurality of sub-cores, an error in response to receiving the inconsistent result; and

sending, by the plurality of sub-cores, a new plurality of residues to the code analyzer.

21. The method of claim 18 , wherein performing the set of operations comprises:

accessing, by the code analyzer, a memory address represented by the code word in response a determination that the memory address code is consistent and the code word being the memory address code.

22. The method of claim 21 , wherein performing the set of operations further comprises:

sending data accessed from the memory address in the memory to the plurality of sub-cores for data processing.

23. The method of claim 21 , wherein performing the set of operations comprises:

performing, by the code analyzer, a condition test based on a condition for the code word using the plurality of residues in response to a determination that the plurality of residues are consistent and the code word being the data code; and

sending, by the code analyzer, a test result based on the condition test to the plurality of sub-cores.

24. The method of claim 23 further comprising:

fetching, by the plurality of sub-cores, a next instruction based on the test result.