IP Library Granted Patent US 9,641,134
Granted Patent B2
US 9,641,134 · App. 14/832,910 · Granted May 2, 2017

Circuit for reducing pop noise

Inventors: Emmanuel Grand (Le Touvet, FR); Sébastien Genevey (Gieres, FR); Arthur Veith (Grenoble, FR); Paul Giletti (Grenoble, FR)
Assignee: Dolphin Integration
H03F1/26H03F1/305H03F3/185H03F3/45179H03F2200/03H03F2200/129
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Quick Facts
Patent No.
US 9,641,134
App. No.
14/832,910
Granted
May 2, 2017
Kind
B2
Abstract

The invention concerns an amplifier circuit comprising: an amplifier having a first input coupled to an input node of the amplifier circuit via a first resistor and an output coupled to a load via a coupling capacitor, the output being coupled to the first input via a second resistor; and a current ramp generator adapted to supply a current ramp to the first input of the amplifier during a power up phase or power down phase of the amplifier circuit to control the rate of charge or discharge of the coupling capacitor.

Claims (28)

1. An amplifier circuit comprising:

an amplifier having a first input coupled to an input node of the amplifier circuit via a first resistor and an output coupled to a load via a coupling capacitor, the output being coupled to the first input via a second resistor; and

a current ramp generator adapted to supply a linear or non-linear current ramp to the first input of the amplifier during a power up phase of the amplifier circuit to control the rate of charge or discharge of the coupling capacitor, the linear or non-linear current ramp starting at a first level and falling to a second level.

2. The amplifier circuit of claim 1 , wherein during a power down phase of the amplifier circuit the current ramp generator is adapted to supply a further linear or non-linear current ramp to the first input of the amplifier, the further linear or non-linear current ramp starting at the second level and rising to the first level.

3. The amplifier circuit of claim 1 , wherein the first level is high enough to cause saturation of the amplifier.

4. The amplifier circuit of claim 1 , wherein the second level is equal to or less than 1 μA.

5. The amplifier circuit of claim 1 , wherein the linear or non-linear current ramp has a gradient that results in a voltage gradient at the output of the amplifier circuit of at least 1 V/s.

6. The amplifier circuit of claim 1 , wherein the current ramp generator is adapted to convert a first voltage ramp into the linear or non-linear current ramp.

7. The amplifier circuit of claim 6 , wherein the current ramp generator comprises a differential pair, a first of the transistors of the differential pair being controlled by the first voltage ramp.

8. The amplifier circuit of claim 7 , wherein a second of the transistors of the differential pair is controlled by a second voltage ramp having a gradient of opposite sign to the first voltage ramp.

9. The amplifier circuit of claim 1 , wherein the amplifier is coupled in an inverting amplifier configuration.

10. The amplifier circuit of claim 1 , wherein the input node of the amplifier circuit couples to a digital-to-analog converter (DAC) and receives an input signal from the DAC.

11. The amplifier circuit of claim 10 , wherein the current ramp generator is coupled between the first and second resistors.

12. An amplifier circuit comprising:

an amplifier having a first input coupled to an input node of the amplifier circuit via a first resistor and an output coupled to a load via a coupling capacitor, the output being coupled to the first input via a second resistor; and

a current ramp generator adapted to supply a linear or non-linear current ramp to the first input of the amplifier during a power down phase of the amplifier circuit to control the rate of charge or discharge of the coupling capacitor, the linear or non-linear current ramp starting at a second level and rising to a first level.

13. The amplifier circuit of claim 12 , wherein the first level is high enough to cause saturation of the amplifier.

14. The amplifier circuit of claim 12 , wherein the second level is equal to or less than 1 μA.

15. The amplifier circuit of claim 12 , wherein the input node of the amplifier circuit couples to a digital-to-analog converter (DAC) and receives an input signal from the DAC.

16. The amplifier circuit of claim 15 , wherein the current ramp generator is coupled between the first and second resistors.

17. A method of powering up an amplifier circuit, comprising:

supplying a linear or non-linear current ramp to a first input of an amplifier of the amplifier circuit, the first input being coupled to an input node of the amplifier circuit via a first resistor an output of the amplifier being coupled to a load via a coupling capacitor and to the first input via a second resistor, wherein the linear or non-linear current ramp starts at a first level and falls to a second level and controls the rate of charge or discharge of the coupling capacitor; and

applying an input signal to the input node of the amplifier circuit.

18. The method of claim 17 , further comprising generating the linear or non-linear current ramp by a current ramp generator and generating the input signal by a digital-to-analog converter (DAC).

19. A method of powering down an amplifier circuit, comprising:

supplying a linear or non-linear current ramp to a first input of an amplifier of the amplifier circuit, the first input being coupled to an input node of the amplifier circuit via a first resistor an output of the amplifier being coupled to a load via a coupling capacitor and to the first input via a second resistor, wherein the linear or non-linear current ramp starts at a second level and rises to a first level and controls the rate of charge or discharge of the coupling capacitor; and

applying an input signal to the input node of the amplifier circuit.

20. The method of claim 19 , further comprising generating the linear or non-linear current ramp by a current ramp generator and generating the input signal by a digital-to-analog converter (DAC).

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 69809 FRAME 7. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 15, 2025
From: DOLPHIN DESIGN
To: DOLPHIN SEMICONDUCTOR
Reel/Frame 069900/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2025
From: DOLPHIN DESIGN
To: DOPHIN SEMCONDUCTOR
Reel/Frame 069809/0007 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2024
From: DOLPHIN DESIGN
To: DOLPHIN SEMICONDUCTOR
Reel/Frame 069590/0911 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2021
From: DOLPHIN INTEGRATION
To: DOLPHIN DESIGN
Reel/Frame 056753/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2015
From: GRAND, EMMANUEL; GENEVEY, SÉBASTIEN; VEITH, ARTHUR; GILETTI, PAUL
To: DOLPHIN INTEGRATION
Reel/Frame 036970/0720 →
Priority Claims (1)
FR 14 57987 · Aug 26, 2014 · national
Continuity (1)
Related Publication 20160065143A1 · Mar 3, 2016