IP Library Granted Patent US 9,727,067
Granted Patent B2
US 9,727,067 · App. 14/833,418 · Granted Aug 8, 2017

Charging device including regulator circuit and integrated circuit

Inventors: Akira Fujiwara (Kyoto, JP); Takashi Kimura (Kyoto, JP)
Assignee: ROHM CO., LTD.
G05F1/59
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Quick Facts
Patent No.
US 9,727,067
App. No.
14/833,418
Granted
Aug 8, 2017
Kind
B2
Abstract

A regulator circuit includes: a regulator part configured to generate a constant internal power supply voltage based on an external power supply voltage; a connection port configured to receive power from the regulator part and to be connected to a connection cable having a predetermined cable resistance, the connection cable is configured to electrically connect the connection port to an external device; a current detecting part configured to detect a power supply current when the connection cable is connected to the connection port; and a voltage compensation part configured to compensate a voltage corresponding to a voltage drop due to the cable resistance according to a current value detected by the current detecting part.

Claims (33)

1. A regulator circuit comprising:

a regulator part configured to generate a constant internal power supply voltage based on an external power supply voltage;

a connection port configured to receive power from the regulator part and to be connected to a connection cable having a predetermined cable resistance, the connection cable is configured to electrically connect the connection port to an external device;

a current detecting part configured to detect a power supply current when the connection cable is connected to the connection port; and

a voltage compensation part configured to compensate a voltage corresponding to a voltage drop due to the cable resistance according to a current value detected by the current detecting part,

wherein the current detecting part includes a current detecting transistor,

wherein the voltage compensation part includes an output transistor which is current mirror-connected with the current detecting transistor, and a compensation amount setting resistor connected to the output side of the current detecting transistor for setting a compensation amount, and

wherein, when a mirror ratio of the current detecting transistor and the output transistor is m1:m2, the transistor sizes are selected to meet the relationship of m1<m2, and

wherein a voltage generated in the compensation amount setting resistor based on a load current output from a source electrode of the current detecting transistor is fed back to a gate electrode of the current detecting transistor to compensate an output voltage of the output transistor which is current mirror-connected with the current detecting transistor.

2. The regulator circuit of claim 1 , wherein each of the current detecting transistor and the output transistor includes a pMOS transistor.

3. The regulator circuit of claim 1 , wherein the connection cable is a cable conforming to the USB standard.

4. The regulator circuit of claim 1 , wherein the compensation amount setting resistor is a variable resistor.

5. A regulator circuit comprising:

a regulator part configured to generate a constant internal power supply voltage based on an external power supply voltage;

a connection port configured to receive power from the regulator part and to be connected to a connection cable having a predetermined cable resistance, the connection cable is configured to electrically connect the connection port to an external device;

a current detecting part configured to detect a power supply current when the connection cable is connected to the connection port; and

a voltage compensation part configured to compensate a voltage corresponding to a voltage drop due to the cable resistance according to a current value detected by the current detecting part,

wherein the current detecting part includes a current detecting transistor,

wherein the voltage compensation part includes an output transistor which is current mirror-connected with the current detecting transistor, and a compensation amount setting resistor connected to the output side of the current detecting transistor for setting a compensation amount, and

wherein, when a mirror ratio of the current detecting transistor and the output transistor is m1:m2, the transistor sizes are selected to meet the relationship of m1<m2, and

wherein the resistance (Rcal) of the compensation amount setting resistor is determined according to the following equation:

R cal= R cable× A ×(( R 1 +R 2)/( R 1)×( Rf 2/( Rf 1 +Rf 2))

where Rcable denotes the cable resistance, A denotes a mirror ratio, R 1 and R 2 denote resistance of voltage dividing resistors connected to a gate electrode of the current detecting transistor, and Rf 1 and Rf 2 denote resistance of reference resistors connected to the output side of the output transistor.

6. An integrated circuit comprising a regulator circuit which includes:

a regulator part configured to generate a constant internal power supply voltage based on an external power supply voltage;

a connection port configured to receive power from the regulator part and to be connected to a connection cable having a predetermined cable resistance, the connection cable is configured to electrically connect the connection port to an external device;

a current detecting part configured to detect a power supply current when the connection cable is connected to the connection port; and

a voltage compensation part configured to compensate a voltage corresponding to a voltage drop due to the cable resistance according to a current value detected by the current detecting part,

wherein the current detecting part includes a current detecting transistor,

wherein the voltage compensation part includes an output transistor which is current mirror-connected with the current detecting transistor, and a compensation amount setting resistor connected to the output side of the current detecting transistor for setting a compensation amount, and

wherein, when a mirror ratio of the current detecting transistor and the output transistor is m1:m2, the transistor sizes are selected to meet the relationship of m1<m2, and

wherein a voltage generated in the compensation amount setting resistor based on a load current output from a source electrode of the current detecting transistor is fed back to a gate electrode of the current detecting transistor to compensate an output voltage of the output transistor which is current mirror-connected with the current detecting transistor.

7. The integrated circuit of claim 6 , further comprising a DC/DC converter configured to convert an external DC voltage to a predetermined voltage, wherein a DC voltage converted by the DC/DC converter is input to the regulator circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2015
From: FUJIWARA, AKIRA; KIMURA, TAKASHI
To: ROHM CO., LTD.
Reel/Frame 036554/0423 →
Priority Claims (1)
JP 2014-170333 · Aug 25, 2014 · national
Continuity (1)
Related Publication 20160054749A1 · Feb 25, 2016