High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
View Patent ↗A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.
1. A multilayer structure comprising:
a silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a bulk region resistivity between 1000 Ohm-cm and about 100,000 Ohm-cm;
a semiconductor nitride layer in contact with the front surface of the silicon wafer handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof;
a dielectric layer in contact with the semiconductor nitride layer; and
a silicon device layer in contact with the dielectric layer.
2. The multilayer structure of claim 1 wherein the silicon wafer handle substrate comprises a wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.
3. The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between 1000 ohm cm and about 10,000 Ohm-cm.
4. The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.
5. The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.
6. The multilayer structure of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.
7. The multilayer structure of claim 1 wherein the semiconductor nitride layer comprises crystalline semiconductor nitride selected from the group consisting of aluminum nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof.
8. A multilayer structure comprising:
a semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the semiconductor handle substrate and the other of which is a back surface of the semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the semiconductor handle substrate, and a bulk region between the front and back surfaces of the semiconductor handle substrate, wherein the semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
a semiconductor nitride layer in contact with the front surface of the semiconductor handle substrate, wherein the semiconductor nitride layer comprises amorphous semiconductor nitride selected from the group consisting of aluminum nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof;
a dielectric layer in contact with the semiconductor nitride layer; and
a semiconductor device layer in contact with the dielectric layer.
9. The multilayer structure of claim 1 wherein the semiconductor nitride layer comprises aluminum nitride.
10. The multilayer structure of claim 1 wherein the semiconductor nitride layer comprises indium nitride.
11. The multilayer structure of claim 1 wherein the semiconductor nitride layer comprises gallium nitride.
12. The multilayer structure of claim 1 wherein the semiconductor nitride layer has an average thickness of between about 1 nanometer and about 2000 nanometers.
13. The multilayer structure of claim 1 wherein the semiconductor nitride layer has an average thickness of between about 5 nanometers and about 2000 nanometers.
14. The multilayer structure of claim 1 wherein the semiconductor nitride layer has an average thickness of between about 5 nanometers and about 1000 nanometers.
15. The multilayer structure of claim 1 wherein the semiconductor nitride layer has an average thickness of between about 5 nanometers and about 500 nanometers.
16. The multilayer structure of claim 1 wherein the semiconductor nitride layer has an average thickness of between about 5 nanometers and about 200 nanometers.
17. The multilayer structure of claim 1 wherein the dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof.