Patent Assignment
Reel/Frame 046327/0001
Assignment of Assignor's Interest
Recorded: 2018-06-07
Pages: 59
Assignors
SUNEDISON SEMICONDUCTOR LIMITED
Executed: 2018-06-06
MEMC JAPAN LIMITED
Executed: 2018-06-06
MEMC ELECTRONIC MATERIALS S.P.A.
Executed: 2018-06-06
Assignee
GLOBALWAFERS CO., LTD.
NO. 8. INDUSTRIAL EAST ROAD, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, R.O.C., TAIWAN
Covered Properties
(268)
Systems and Methods for Production of Low Oxygen Content Silicon
PCT:
PCT/US2016/064448 ↗
High Resistivity Silicon-on-Insulator Substrate Comprising a Charge Trapping Layer Formed on a Substrate with a Rough Surface
PCT:
PCT/US2017/015813 ↗
Semiconductor on Insulator Structure Comprising a Buried High Resistivity Layer
PCT:
PCT/US2017/017756 ↗
Method of Manufacturing a Semiconductor on Insulator Structure by a Pressurized Bond Treatment
PCT:
PCT/US2017/020614 ↗
Semiconductor on Insulator Structure Comprising a Low Temperature Flowable Oxide Layer and Method of Manufacture Thereof
PCT:
PCT/US2017/020619 ↗
Semiconductor on Insulator Structure Comprising a Plasma Oxide Layer and Method of Manufacture Thereof
PCT:
PCT/US2017/020623 ↗
Semiconductor on Insulator Structure Comprising a Plasma Nitride Layer and Method of Manufacture Thereof
PCT:
PCT/US2017/020634 ↗
Direct Formation of Hexagonal Boron Nitride on Silicon Based Dielectrics
PCT:
PCT/US2017/030124 ↗
High Resistivity Single Crystal Silicon Ingot and Wafer Having Improved Mechanical Strength
PCT:
PCT/US2017/036061 ↗
High Resistivity Silicon-on-Insulator Substrate Having Enhanced Charge Trapping Efficiency
PCT:
PCT/US2017/055722 ↗
Process for the Removal of Copper and Other Metallic Impurities from Silicon
Patent:
6,482,269 →
Application:
09/082,906 →
Electrical Resistance Heater for Crystal Growing Apparatus
Patent:
6,093,913 →
Application:
09/092,391 →
Collector for an Automated on-Line Bath Analysis System
Patent:
6,210,640 →
Application:
09/093,520 →
Process and Appratus for Preparation of Silicon Crystals with Reduced Metal Content
Patent:
6,183,553 →
Application:
09/097,779 →
Susceptor for Barrel Reactor
Patent:
6,129,048 →
Application:
09/107,728 →
Continuous Oxidation Process for Crystal Pulling Apparatus
Patent:
6,039,801 →
Application:
09/167,747 →
Method and System for Controlling Growth of a Silicon Crystal
Patent:
6,171,391 →
Application:
09/172,546 →
Tungsten Doped Crucible and Method for Preparing Same
Patent:
6,187,089 →
Application:
09/245,238 →
An Epitaxial Silicon Wafer with Intrinsic Gettering
Patent:
6,284,384 →
Application:
09/250,908 →
Heat Shield Assembly for Crystal Puller
Patent:
6,197,111 →
Application:
09/258,478 →
Method for Processing a Semiconductor Wafer
Patent:
6,227,944 →
Application:
09/276,278 →
Method and System of Controlling Taper Growth in a Semiconductor Crystal Growth Process
Patent:
6,241,818 →
Application:
09/287,916 →
Process for Preparing Defect Free Silicon Crystals Which Allows for Variability in Process Conditions
Process for Growth of Defect Free Silicon Crystals of Arbitrarily Large Diameters
Method for the Separation, Regeneration and Refuse of an Exhausted Glycol-Based Slurry
Patent:
6,231,628 →
Application:
09/345,934 →
Process for Fabricating Semiconductor Wafers with External Gettering
Patent:
6,338,805 →
Application:
09/352,980 →
Non-Uniform Minority Carrier Lifetime Distributions in High Performance Silicon Power Devices
Patent:
6,828,690 →
Application:
09/366,850 →
Non-Oxygen Precipitating Czochralski Silicon Wafers
Patent:
6,336,968 →
Application:
09/379,383 →
Process for Preparing an Ideal Oxygen Precipitating Silicon Wafer
Patent:
6,191,010 →
Application:
09/384,669 →
Thermally Annealed Wafers Having Improved Internal Gettering
Patent:
6,361,619 →
Application:
09/385,108 →
Silicon on Insulator Structure from Low Defect Density Single Crystal Silicon
Patent:
6,236,104 →
Application:
09/387,288 →
Method of Processing Semiconductor Wafers to Build in Back Surface Damage
Patent:
6,214,704 →
Application:
09/404,428 →
Thermally Annealed, Low Defect Density Single Crystal Silicon
Patent:
6,416,836 →
Application:
09/416,998 →
Epitaxial Silicon Wafers Substantially Free of Grown - in Defects
Patent:
6,284,039 →
Application:
09/417,610 →
Method of Controlling Growth of a Semiconductor Crystal to Automatically Transition from Taper Growth to Target Diameter Growth
Patent:
6,203,611 →
Application:
09/421,187 →
Method of Determining Performance Characteristics of Polishing Pads
Patent:
6,293,139 →
Application:
09/432,928 →
Semiconductor Wafer Manufacturing Process
Continuous oxidation process for crystal pulling Apparatus
Patent:
6,315,828 →
Application:
09/489,481 →
Method of Controlling Diameter of a Silicon Crystal in a Locked Seed Lift Growth Process
Patent:
6,776,840 →
Application:
09/502,340 →
Process for producing a silicon melt
Patent:
6,344,083 →
Application:
09/503,566 →
Semiconductor Wafer Manufacturing Process
Patent:
6,376,335 →
Application:
09/506,105 →
Silicon wafering process flow
Patent:
6,294,469 →
Application:
09/512,111 →
Barium doping of molten silicon for use in crystal growing process
Patent:
6,319,313 →
Application:
09/521,288 →
Strontium doping of molten silicon for use in crystal growing process
Patent:
6,350,312 →
Application:
09/521,525 →
Modified Susceptor for Use in Chemical Vapor Deposition Process
Patent:
6,444,027 →
Application:
09/566,890 →
Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
Patent:
6,339,016 →
Application:
09/607,389 →
Method and Apparatus for Forming a Silicon Wafer with a Denuded Zone
Patent:
6,599,815 →
Application:
09/607,391 →
Non-Contaminating Gas-Tight Valve for Semiconductor Applications
Patent:
6,435,474 →
Application:
09/608,304 →
Radio frequency identification system and method for tracking silicon wafers
Patent:
6,330,971 →
Application:
09/677,909 →
Polishing Apparatus, Polishing Head and Method
A Process for the Preparation of an Ideal Oxygen Precipitating Silicon Wafer Having an Asymmetrical Vacancy Concentration Profile Capable of Forming an Enhanced Denuded Zone
Patent:
6,579,779 →
Application:
09/704,900 →
Low Defect Density, Ideal Oxygen Precipitating Silicon
Patent:
6,555,194 →
Application:
09/705,092 →
Silicon on insulator structure having a low defect density handle wafer and process for the preparation thereof
Process for Growing Silicon Crystals Which Allows for Variability in Process Conditions While Suppressing the Formation of Agglomerated Intrinsic Point Defects
Process for Preparing Low Defect Density Silicon Using High Growth Rates
An Epitaxial Wafer Substantially Free of Grown-in Defects
Crystal Puller and Method for Growing Monocrystalline Silicon Ingots
Method and Apparatus for Processing a Semiconductor Wafer Using Novel Final Polishing Method
Process for the Preparation of Non-Oxygen Precipitating Czochralski Silicon Wafers
Method for Controlling Growth of a Silicon Crystal to Minimize Growth Rate and Diameter Deviations
Process for Reclaiming Semiconductor Wafers and Reclaimed Wafers
Granular Semiconductor Material Transport System and Process
SOI structure having a device layer which is vacancy dominated and substantially free fo agglomerated vacancy type defects
Single Crystal Silicon Having Improved Gate Oxide Integrity
Low Defect Density Silicon Having a Vacancy-Dominated Core Substantially Free of Oxidation Induced Stacking Faults
Process for Producing Thermally Annealed Wafers Having Improved Internal Gettering
Thermal Annealing Process for Producing Low Defect Density Single Crystal Silicon
Thermal Annealing Process for Producing Silicon Wafers with Improved Surface Characteristics
Control of Oxygen Precipitate Formation in High Resistivity Cz Silicon
Silicon on Insulator Struture Having an Epitaxial Layer and Intrinsic Gettering
Controlled Neck Growth Process for Single Crystal Silicon
Non-Oxygen Precipitating Czochralski Silicon Wafers
Modified Susceptor for Use in Chemical Vapor Deposition Process
Method of Polishing Wafers
Patent:
6,878,302 →
Application:
10/239,669 →
Analytical Method to Measure Nitrogen Concentration in Single Crystal Silicon
Crystal Puller for Growing Monocrystalline Silicon Ingots
A Single Crystal Silicon Ingot Having a High Arsenic Concentration
Process for Growing a Silicon Crystal Segment Substantially Free from Agglomerated Intrinsic Point Defects Which Allows for Variability in the Process Conditions
Wire Saw and Process for Slicing Multiple Semiconductor Ingots
Patent:
6,941,940 →
Application:
10/296,919 →
Ideal Oxygen Precipitating Silicon Wafers with Nitrogen/Carbon Stabilized Oxygen Precipitate Nucleation Centers and Process for Making the Same
Process for Producing Low Defect Density, Ideal Oxygen Precipitating Silicon
Semiconductor Wafer, Polishing Apparatus and Method
Patent:
7,137,874 →
Application:
10/432,513 →
Process for Cooling a Silicon Ingot Having a Vacancy Dominated Region to Produce Defect Free Silicon
Single Crystal Silicon Wafer Having an Epitaxial Layer Substantially Free from Grown-in Defects
Process for the Preparation of an Ideal Oxygen Precipitating Silicon Wafer Capable of Forming an Enhanced Denuded Zone
Fluid Sealing System for a Crystal Puller
Method for Treating an Exhausted Glycol-Based Slurry
Wafer Clamping Device for a Double Side Grinder
Process for Preparing a Stabilized Ideal Oxygen Precipitating Silicon Wafer
Process for Preparing Single Crystal Silicon Using Crucible Rotation to Control Temperature Gradient
Process for Metallic Contamination Reduction in Silicon Wafers
Partially Devitrified Crucible
High Purity Silicon Carbide Structures
Process for Making Non-Uniform Minority Carrier Lifetime Distribution in High Performance Silicon Power Devices
Systems and Methods for Measuring and Reducing Dust in Granular Material
Low Defect Density Silicon Having a Vacancy-Dominated Core Substantially Free of Oxidation Induced Stacking Faults
Controlling Melt-Solid Interface Shape of a Growing Silicon Crystal Using a Variable Magnetic Field
Electromagnetic Pumping of Liquid Silicon in a Crystal Growing Process
Semiconductor Wafer Boat for a Vertical Furnace
Patent:
7,033,168 →
Application:
11/041,593 →
Method for Controlling of Thermal Donor Formation in High Resistivity Cz Silicon
Process for Preparing Single Crystal Silicon Having Improved Gate Oxide Integrity
Modified Susceptor for Barrel Reactor
Silicon Wafer Etching Process and Composition
Melter Assembly and Method for Charging a Crystal Forming Apparatus with Molten Source Material
Melter Assembly and Method for Charging a Crystal Forming Apparatus with Molten Source Material
Melter Assembly and Method for Charging a Crystal Forming Apparatus with Molten Source Material
Arsenic and Phosphorus Doped Silicon Wafer Substrates Having Intrinsic Gettering
Silicon Structures with Improved Resistance to Radiation Events
High Resistivity Silicon Structure and a Process for the Preparation Thereof
Method of Polishing a Semiconductor Wafer
Double Side Wafer Grinder and Methods for Assessing Workpiece Nanotopology
Nitrogen-Doped Silicon Substantially Free of Oxidation Induced Stacking Faults
Processes for the Purification of Trichlorosilane and Silicon Tetrachloride
Controlling Agglomerated Point Defect and Oxygen Cluster Formation Induced by the Lateral Surface of a Silicon Single Crystal During Cz Growth
Silicon Material with Controlled Agglomerated Point Defects and Oxygen Clusters Induced by the Lateral Surface
Controlling Melt-Solid Interface Shape of a Growing Silicon Crystal Using a Variable Magnetic Field
Method for Purifying Silicon Carbide Coated Structures
Non-Uniform Minority Carrier Lifetime Distributions in High Performance Silicon Power Devices
Dressing a Wafer Polishing Pad
Methods for Producing Smooth Wafers
Epitaxial Barrel Susceptor Having Improved Thickness Uniformity
Semiconductor Wafer Carrier Blade
Nanotopography Control and Optimization Using Feedback from Warp Data
Silicon Wafer Etching Compositions
Method and Device for Feeding Arsenic Dopant into a Silicon Crystal Growing Apparatus
Semiconductor Wafer Polishing Apparatus and Method of Polishing
Low Thermal Mass Semiconductor Wafer Support
Method and Device for Continuously Measuring Silicon Island Elevation
Patent:
7,573,587 →
Application:
12/197,669 →
Wafer Holder for Supporting a Semiconductor Wafer During a Thermal Treatment Process
Arsenic and Phosphorus Doped Silicon Wafer Substrates Having Intrinsic Gettering
System and Method for Dressing a Wafer Polishing Pad
Methods for Etching the Edge of a Silicon Wafer
Edge Etched Silicon Wafers
Methods for Preparing a Semiconductor Structure for Use in Backside Illumination Applications
Controlling a Melt-Solid Interface Shape of a Growing Silicon Crystal Using an Unbalanced Magnetic Field and Iso-Rotation
Generating a Pumping Force in a Silicon Melt by Applying a Time-Varying Magnetic Field
Method for Feeding Arsenic Dopant into a Silicon Crystal Growing Apparatus
Method for Assessing Workpiece Nanotopology Using a Double Side Wafer Grinder
Methods for Generating Representations of Flatness Defects on Wafers
Systems for Generating Representations of Flatness Defects on Wafers
Systems for Weighing a Pulled Object
Systems for Weighing a Pulled Object Having a Changing Weight
Wafer Support Ring
Semiconductor and Solar Wafers
Methods and Systems for Adjusting Operation of a Wafer Grinder Using Feedback from Warp Data
Methods of Grinding Semiconductor Wafers Having Improved Nanotopology
Process for Annealing Semiconductor Wafers with Flat Dopant Depth Profiles
Patent:
8,153,538 →
Application:
12/964,143 →
Methods for Monitoring the Amount of Contamination Imparted into Semiconductor Wafers During Wafer Processing
Methods for Processing Silicon on Insulator Wafers
Method for the Preparation of a Multi-Layered Crystalline Structure
Process and System for the Purification of Trichlorosilane and Silicon Tetrachloride
Semiconductor Wafers with Reduced Roll-Off and Bonded and Unbonded Soi Structures Produced from Same
Methods for Reducing the Width of the Unbonded Region in Soi Structures
Hydrostatic Pad Pressure Modulation in a Simultaneous Double Side Wafer Grinder
Bulk Silicon Wafer Product Useful in the Manufacture of Three Dimensional Multigate Mosfets
Method and System for Stripping the Edge of a Semiconductor Wafer
Methods for in-Situ Passivation of Silicon-on-Insulator Wafers
Methods for Preparing a Semiconductor Wafer with High Thermal Conductivity
Low Thermal Mass Semiconductor Wafer Plate
Low Thermal Mass Semiconductor Wafer Boat
Methods for Producing Crucibles with a Reduced Amount of Bubbles
Methods for Producing Crucibles with a Reduced Amount of Bubbles
Methods for Monitoring the Amount of Metal Contamination in a Process
Methods for Reducing the Metal Content in the Device Layer of Soi Structures and Soi Structures Produced by Such Methods
Reactor Apparatus and Methods for Reacting Compounds
Method of Manufacturing Silicon-On-Insulator Wafers
Method for Machining Seed Rods for Use in a Chemical Vapor Deposition Polysilicon Reactor
Systems and Methods for Cleaving A Bonded Wafer Pair
Tool for Harvesting Polycrystalline Silicon-Coated Rods from a Chemical Vapor Deposition Reactor
Methods for Producing Silicon on Insulator Structures Having High Resistivity Regions in the Handle Wafer
Methods for Fabricating a Semiconductor Wafer Processing Device
Methods and Systems for Monitoring and Controlling Silicon Rod Temperature
Processes for the Purification of Trichlorosilane or Silicon Tetrachloride
Direct Formation of Graphene on Semiconductor Substrates
Methods for Cleaving a Bonded Wafer Structure
Clamping Apparatus for Cleaving a Bonded Wafer Structure
Method of Loading a Charge of Polysilicon into a Crucible
Air Pocket Detection Methods and Systems
Symmetry Based Air Pocket Detection Methods and Systems
Methods For Mounting An Ingot On A Wire Saw
Systems and Methods for Reducing Dust in Granular Material
Single Side Polishing Using Shape Matching
Gas Distribution Plate for Chemical Vapor Deposition Systems and Methods of Using Same
Inject Insert Liner Assemblies for Chemical Vapor Deposition Systems and Methods of Using Same
Susceptor Assemblies for Supporting Wafers in a Reactor Apparatus
Methods for Reacting Compounds
Direct and Sequential Formation of Monolayers of Boron Nitride and Graphene on Substrates
Oxygen Precipitation in Heavily Doped Silicon Wafers Sliced from Ingots Grown by the Czochralski Method
Production of High Precipitate Density Wafers by Activation of Inactive Oxygen Precipitate Nuclei
Systems and Methods for Interferometric Phase Measurement
Double Side Polisher with Platen Parallelism Control
Method for Low Temperature Layer Transfer in the Preparation of Multilayer Semiconductor Devices
Method and System for Full Resolution Real-Time Data Logging
Method and System for a Meta-Recipe Control Software Architecture
Methods and Systems for Deterministic and Multithreaded Script Objects and Script Engine
Methods and Systems for Preventing Unsafe Operations
Processes and Apparatus for Preparing Heterostructures with Reduced Strain by Radial Distension
Processes and Apparatus for Preparing Heterostructures with Reduced Strain by Radial Compression
Apparatus for Stressing Semiconductor Substrates
Liner Assemblies for Substrate Processing Systems
Semiconductor-On-Insulator Wafer Manufacturing Method for Reducing Light Point Defects and Surface Roughness
Center Flex Single Side Polishing Head
Application:
14/292,837 →
Publication:
US 2014/0357161
Systems and Methods for Controlling Temperatures in an Epitaxial Reactor
Method to Delineate Crystal Related Defects
Method and System for Arranging Numeric Data for Compression
Direct Formation of Graphene on Semiconductor Substrates
Method of Manufacturing High Resistivity Soi Substrate with Reduced Interface Conducitivity
Center Flex Single Side Polishing Head Having Recess and Cap
Method of Manufacturing High Resistivity Soi Wafers with Charge Trapping Layers Based on Terminated Si Deposition
Direct and Sequential Formation of Monolayers of Boron Nitride and Graphene on Substrates
Methods for Post-Epitaxial Warp Prediction and Control
Gas Doping Systems for Controlled Doping of a Melt of Semiconductor or Solar-Grade Material
Application:
14/774,310 →
Publication:
US 2016/0017513
Nitrogen Doped and Vacancy Dominated Silicon Ingot and Thermally Treated Wafer Formed Therefrom Having Radially Uniformly Distributed Oxygen Precipitation Density and Size
High Resistivity Silicon-on-Insulator Wafer Manufacturing Method for Reducing Substrate Loss
High Resistivity Silicon-on-Insulator Wafer Manufacturing Method for Reducing Substrate Loss
Method of Manufacturing High Resistivity Silicon-on-Insulator Substrate
Clamping Apparatus for Cleaving a Bonded Wafer Structure and Methods for Cleaving
Methods for Producing Low Oxygen Silicon Ingots
Dopant Feeding Device for Dispensing Dopant
Handle Substrate for Use in Manufacture of Semiconductor-on-Insulator Structure and Method of Manufacturing Thereof
Substrate Processing Systems Having Multiple Gas Flow Controllers
High Resistivity Soi Wafers and a Method of Manufacturing Thereof
Methods for Preparing Layered Semiconductor Structures
Epitaxy Reactor and Susceptor System for Improved Epitaxial Wafer Flatness
Methods and Systems for Polishing Pad Control
Methods for Preparing Layered Semiconductor Structures and Related Bonded Structures
Application:
15/191,975 →
Publication:
US 2017/0025306
Wafer Nanotopography Metrology for Lithography Based on Thickness Maps
Crystal Growing Systems and Methods Including a Transparent Crucible
Semiconductor Substrate Polishing Methods and Slurries and Methods for Manufacturing Silicon on Insulator Structures
Methods and System for Controlling a Surface Profile of a Wafer
Semiconductor Wafer Support Ring for Heat Treatment
Crystal Pulling Systems and Methods for Producing Monocrystalline Ingots with Reduced Edge Band Defects
Crystal Pulling System and Method for Inhibiting Precipitate Build-Up in Exhaust Flow Path
Semiconductor Substrate Polishing Methods with Dynamic Control
Seed Chuck Assemblies and Crystal Pulling Systems for Reducing Deposit Build-Up During Crystal Growth Process
Process Flow for Manufacturing Semiconductor on Insulator Structures in Parallel
Semiconductor on Insulator Structure Comprising a Sacrificial Layer and Method of Manufacture Thereof
Surface Photovoltage Calibration Standard
High Resistivity Semiconductor-on-Insulator Wafer and a Method of Manufacturing
A Method of Manufacturing High Resistivity Semiconductor-on-Insulator Wafers with Charge Trapping Layers
HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
Systems and Methods for Performing Phase Shift Interferometry While a Wafer Is Vibrating
Systems and Methods for Performing Epitaxial Smoothing Processes on Semiconductor Structures
Manufacture of Group Iiia-Nitride Layers on Semiconductor on Insulator Structures
Preparation of Silicon-Germanium-on-Insulator Structures
Application:
15/540,859 →
Publication:
US 2018/0005872
Feed Material System for a Czochralski Crystal Growth System Comprising a Feed Channel Movable Between a Retracted and Extended Position and Method of Using Same
Application:
15/549,919 →
Publication:
US 2018/0030614
Method of Depositing Charge Trapping Polycrystalline Silicon Films on Silicon Substrates with Controllable Film Stress
Methods for Controlled Doping of a Melt Including Introducing Liquid Dopant Below a Surface of the Melt
Thermally Stable Charge Trapping Layer for Use in Manufacture of Semiconductor-on-Insulator Structures
A Method of Manufacturing Silicon Germanium-On-Insulator
Method of Manufacturing Semiconductor-On-Insulator
Methods for Processing Semiconductor Wafers Having a Polycrystalline Finish
High Resistivity Silicon-on-Insulator Substrate Comprising an Isolation Region
Methods for Producing Single Crystal Silicon Ingots with Reduced Seed End Oxygen
Application:
15/662,844 →
Publication:
US 2018/0030615
Method of Manufacturing High Resistivity Soi Wafers with Charge Trapping Layers Based on Terminated Si Deposition
High Resistivity Silicon-on-Insulator Substrate Having Enhanced Charge Trapping Efficiency
Systems for Selectively Feeding Chunk Polysilicon or Granular Polysilicon in a Crystal Growth Chamber
Methods for Processing Semiconductor Wafers Having a Polycrystalline Finish
Cvd Apparatus
Epitaxial Growth of Defect-Free, Wafer-Scale Single-Layer Graphene on Thin Films of Cobalt
Manufacturing Method of Smoothing a Semiconductor Surface
Handle Substrate for Use in Manufacture of Semiconductor-on-Insulator Structure and Method of Manufacturing Thereof
High Resistivity Silicon-on-Insulator Wafer Manufacturing Method for Reducing Substrate Loss
High Resistivity Silicon-on-Insulator Substrate Comprising an Isolation Region
Semiconductor on Insulator Structure Comprising a Sacrificial Layer and Method of Manufacture Thereof
Crystal Growing Systems and Methods Including a Transparent Crucible
Methods for Producing Low Oxygen Silicon Ingots
High Resistivity Silicon-on-Insulator Substrate Comprising a Charge Trapping Layer Formed by He-N2 Co-Implantation
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
Release of Security Interest
Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
Release of Security Interest
Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
Security Agreement
Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
Release of Security Interest
Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
Release of Security Interest to Reel/Frame: 012280/0161
Mar 17, 2014
From: CITICORP USA, INC.
To: MEMC ELECTRONIC MATERIALS, INC. (NOW KNOWN AS SUNEDISON, INC.); MEMC PASADENA, INC.; PLASMASIL, L.L.C.; SIBOND, L.L.C.
Reel/Frame 032458/0794 →
Assignment of Assignor's Interest
May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
Notice of License Agreement
Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →