Systems for generating representations of flatness defects on wafers
View Patent ↗Systems and computer-readable media having computer-executable components are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
1. A system for generating a representation of flatness defects on a substrate, the system comprising:
a memory area for storing an application program; and
a processor programmed for:
receiving data describing the thickness of the substrate at a plurality of points on the substrate, the substrate divided into a plurality of sites;
defining a reference plane for each of the plurality of sites;
defining, for each of the sites, a lower plane spaced from the reference plane towards the back side of the substrate by a threshold value and an upper plane spaced from the reference plane away from the back side of the substrate by the threshold value;
determining which of the plurality of points on the substrate represents a flatness defect by identifying which of the plurality of points are not disposed between the upper plane and the lower plane; and
generating a graphical representation depicting a location of each of the flatness defects on the substrate, wherein generating the graphical representation of the flatness defects includes differentiating in the graphical representation between points having flatness defects disposed between the lower plane and the back side of the substrate and points having flatness defects disposed above the upper plane.
2. The system of claim 1 further comprising generating a graphical representation of the flatness defects for a plurality of substrates.
3. The system of claim 1 further comprising, before the substrate is divided into a plurality of sites, defining an edge exclusion zone adjacent a circumferential edge of the substrate.
4. The system of claim 3 further comprising dividing the substrate into the plurality of equally sized sites except portions of the substrate where a site would have a geometric center disposed in the edge exclusion zone.
5. The system of claim 1 further comprising altering a substrate processing method based on the graphical representation depicting the location of each of the flatness defects on the substrate.
6. The system of claim 5 wherein the substrate is a semiconductor wafer.
7. One or more non-transitory computer-readable media having computer-executable components for generating a representation of flatness defects on a substrate, the components comprising:
an interface component that when executed by at least one processor cause the at least one processor to receive data describing the thickness of the substrate at a plurality of points on the substrate, the substrate divided into a plurality of sites;
a first definition component that when executed by at least one processor cause the at least one processor to define a reference plane for each of the plurality of sites;
a second definition component that when executed by at least one processor cause the at least one processor to define, for each of the sites, a lower plane spaced from the reference plane towards a back side of the substrate by a threshold value and an upper plane spaced from the reference plane away from the back side of the substrate by the threshold value;
a determination component that when executed by at least one processor cause the at least one processor to determine which of the plurality of points on the substrate represents a flatness defect by identifying which of the plurality of points are not disposed between the upper plane and the lower plane; and
a generation component that when executed by at least one processor cause the at least one processor to generate a graphical representation depicting a location of each of the flatness defects on the substrate, and differentiate in the graphical representation between points having flatness defects disposed between the lower plane and the back side of the substrate and points having flatness defects disposed above the upper plane.
8. The non-transitory computer-readable media of claim 7 wherein the generation component further comprises generating a graphical representation of the flatness defects for a plurality of substrates.
9. The non-transitory computer-readable media of claim 7 further comprising a third definition component that when executed by at least one processor cause the at least one processor to define, before the substrate is divided into a plurality of sites, an edge exclusion zone adjacent a circumferential edge of the substrate.
10. The non-transitory computer-readable media of claim 9 further comprising a division component that when executed by at least one processor cause the at least one processor to divide the substrate into the plurality of equally sized sites except portions of the substrate where a site would have a geometric center disposed in the edge exclusion zone.
11. The non-transitory computer-readable media of claim 7 further comprising an alteration component that when executed by at least one processor cause the at least one processor to alter a substrate processing method based on the graphical representation depicting the location of each of the flatness defects on the substrate.
12. The non-transitory computer-readable media of claim 11 wherein the substrate is a semiconductor wafer.