IP Library Granted Patent US 7,618,879
Granted Patent B2
US 7,618,879 · App. 11/763,043 · Granted Nov 17, 2009

Non-uniform minority carrier lifetime distributions in high performance silicon power devices

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Quick Facts
Patent No.
US 7,618,879
App. No.
11/763,043
Granted
Nov 17, 2009
Kind
B2
Abstract

This invention is directed to a process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having the desired vacancy concentration profile. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Claims (30)

1. A process for heat-treating a single crystal silicon segment to influence a concentration profile of minority carrier recombination centers in the segment, the silicon segment having a front surface, a back surface, a central plane between the front and back surfaces, a surface layer which comprises the region of the segment between the front surface and a distance, D, measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the segment between the central plane and surface layer, the process comprising:

heat-treating the segment in an atmosphere to form crystal lattice vacancies in the surface and bulk layers;

controlling a cooling rate of the heat-treated segment to produce a segment having a vacancy concentration profile in which a peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment; and,

thermally diffusing platinum atoms into a silicon matrix of the cooled segment such that a platinum concentration profile is substantially dependent upon the vacancy concentration profile.

2. The process of claim 1 wherein said heat-treatment to form crystal lattice vacancies comprises heating the segment to a temperature in excess of about 1175° C. in a non-oxidizing atmosphere.

3. The process of claim 1 wherein said heat-treatment to form crystal lattice vacancies comprises heating the segment to a temperature in excess of about 1200° C. in a non-oxidizing atmosphere.

4. The process of claim 1 wherein said heat-treatment to form crystal lattice vacancies comprises heating the segment to a temperature in the range of about 1200° C. to about 1275° C. in a non-oxidizing atmosphere.

5. The process of claim 1 wherein said cooling rate is at least about 20° C. per second through a temperature range at which crystal lattice vacancies are relatively mobile in silicon.

6. The process of claim 1 wherein said cooling rate is at least about 50° C. per second through a temperature range at which crystal lattice vacancies are relatively mobile in silicon.

7. The process of claim 1 wherein said cooling rate is at least about 100° C. per second through a temperature range at which crystal lattice vacancies are relatively mobile in silicon.

8. The process of claim 1 wherein platinum atoms are thermally diffused into the silicon matrix of the segment by heating the segment to a temperature ranging from about 670 to about 750° C.

9. The process of claim 1 wherein platinum atoms are thermally diffused into the silicon matrix of the segment by heating the segment from about 10 minutes to about 2 hours.

10. The process of claim 1 wherein prior to platinum in-diffusion the heat-treated or cooled segment is subjected to a second heat-treatment in an atmosphere of pure oxygen or pyrogenic steam, a temperature of said second heat-treatment being at least about equal to a temperature of said heat-treatment to form crystal lattice vacancies.

11. The process of claim 1 wherein said heat-treatment to form crystal lattice vacancies comprises the steps of:

(a) subjecting the segment to a first heat-treatment at a temperature of at least about 700° C. in an oxygen containing atmosphere to form a superficial silicon dioxide layer which is capable of serving as a sink for crystal lattice vacancies; and,

(b) subjecting the product of step (a) to a second heat-treatment at a temperature of at least about 1150° C. in an atmosphere having an essential absence of oxygen to form crystal lattice vacancies in the bulk of the silicon segment.

12. A process for heat-treating a single crystal silicon segment to influence a concentration profile of minority carrier recombination centers in the segment, the silicon segment having a front surface and a back surface, the front surface having only a native oxide layer present thereon, and a central plane between the front and back surfaces, the process comprising:

heat-treating the front surface of the segment in a nitriding atmosphere to form crystal lattice vacancies in the segment;

controlling a cooling rate of the heat-treated segment to produce a vacancy concentration profile in the cooled segment in which a maximum concentration is between the front surface and the central plane and nearer to the front surface than the central plane, the vacancy concentration generally increasing from the front surface to the region of maximum concentration and generally decreasing from the region of maximum concentration to the central plane; and,

thermally diffusing platinum atoms into a silicon matrix of the cooled segment such that a platinum concentration profile is substantially dependent upon the vacancy concentration profile.

13. The process of claim 12 wherein said heat-treatment to form crystal lattice vacancies comprises heating the segment to a temperature in excess of about 1175° C. in a non-oxidizing atmosphere.

14. The process of claim 12 wherein said heat-treatment to form crystal lattice vacancies comprises heating the segment to a temperature in the range of about 1200° C. to about 1275° C. in a non-oxidizing atmosphere.

15. The process of claim 12 wherein said cooling rate is at least about 20° C. per second through a temperature range at which crystal lattice vacancies are relatively mobile in silicon.

16. The process of claim 12 wherein said cooling rate is at least about 100° C. per second through a temperature range at which crystal lattice vacancies are relatively mobile in silicon.

17. The process of claim 12 wherein platinum atoms are thermally diffused into the silicon matrix of the segment by heating the segment to a temperature ranging from about 670 to about 750° C.

18. The process of claim 12 wherein platinum atoms are thermally diffused into the silicon matrix of the segment by heating the segment from about 10 minutes to about 2 hours.

19. The process of claim 12 wherein prior to platinum in-diffusion the heat-treated or cooled segment is subjected to a second heat-treatment in an atmosphere of pure oxygen or pyrogenic steam, a temperature of said second heat-treatment being at least about equal to a temperature of said heat-treatment to form crystal lattice vacancies.

20. The process of claim 12 wherein said heat-treatment to form crystal lattice vacancies comprises the steps of:

(a) subjecting the segment to a first heat-treatment at a temperature of at least about 700° C. in an oxygen containing atmosphere to form a superficial silicon dioxide layer which is capable of serving as a sink for crystal lattice vacancies; and,

(b) subjecting the product of step (a) to a second heat-treatment at a temperature of at least about 1150° C. in an atmosphere having an essential absence of oxygen to form crystal lattice vacancies in the bulk of the silicon segment.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
SECURITY AGREEMENT Recorded Apr 1, 2011
From: MEMC ELECTRONIC MATERIALS, INC.; SUNEDISON LLC; SOLAICX
To: BANK OF AMERICA, N.A.
Reel/Frame 026064/0720 →