IP Library Granted Patent US 8,058,173
Granted Patent B2
US 8,058,173 · App. 11/960,236 · Granted Nov 15, 2011

Methods for producing smooth wafers

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Quick Facts
Patent No.
US 8,058,173
App. No.
11/960,236
Granted
Nov 15, 2011
Kind
B2
Abstract

Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.

Claims (61)

1. A method for reducing the surface roughness of a semiconductor wafer having a front surface and a back surface, the method comprising:

rough polishing the front surface and back surface of the wafer, wherein the polishing step does not reduce the roughness of the front surface and back surface of the wafer to below about 1.5 A as measured with scan sizes of about 1 μm × about 1 μm to about 100μm × about 100μm; and

thermally annealing the rough polished wafer at a temperature of at least about 1050° C. for a period of at least about 5 minutes in an atmosphere comprising an inert gas, hydrogen or a mixture thereof, wherein the wafer is not finish polished after the rough polishing step.

2. The method of claim 1 wherein the wafer is thermally annealed at a temperature of no more than about 1350° C.

3. The method of claim 2 wherein the wafer is thermally annealed at a temperature of at least about 1150° C. for a period of at least about 10 minutes to create a substantially void-free region at least about 10 μm in thickness at the front surface of the wafer.

4. The method of claim 2 wherein the wafer is thermally annealed at a temperature of at least about 1200° C. for a period of at least about 1 hour to create a substantially void-free region at least about 10 μm in thickness at the front surface of the wafer.

5. The method of claim 1 wherein the thermal anneal reduces localized light scatterers on the front surface of the wafer caused by scratches, roughness and surface defects and greater than about 45 nm in diameter to no more than about 25.

6. The method of claim 1 wherein the wafer is thermally annealed at a temperature of at least about 1050° C. for a period of at least about 10 minutes.

7. The method of claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to below about 1.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

8. The method of claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to below about 1.5 Å as measured with scan sizes of about 1 μm × about 1μm to about 30 μm × about 30 μm.

9. The method of claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to between about 0.6 Å and about 1.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

10. The method of claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to between about 0.6 Å and about 1.5 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

11. The method of claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to between about 0.7 Å and about 1.5 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

12. The method of claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to about 0.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

13. The method of claim 1 wherein the rough polishing step does not reduce the roughness of the front surface of the wafer to below about 1.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 100 μm × about 100 μm.

14. The method of claim 1 wherein the rough polishing step removes a surface thickness on the front surface of the wafer of between about 1 μm and about 20 μm.

15. The method of claim 1 wherein the thermal anneal reduces the roughness of the back surface of the wafer to below about 1.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

16. The method as set forth in claim 1 wherein the atmosphere in which the polished wafer is thermally annealed comprises an inert gas.

17. The method as set forth in claim 16 wherein the inert gas is argon.

18. The method as set forth in claim 1 wherein the atmosphere in which the polished wafer is thermally annealed consists essentially of an inert gas.

19. The method as set forth in claim 18 wherein the inert gas is argon.

20. The method as set forth in claim 1 wherein the thermal anneal reduces the roughness of the front surface of the wafer to below about 2.5 Å as measured with a scan size of about 100 μm × about 100 μm.

21. A method for reducing the surface roughness of a semiconductor wafer having a front surface and a back surface, the method comprising:

rough polishing the front surface and back surface of the wafer, wherein the polishing step does not reduce the roughness of the front surface and back surface of the wafer to below about 1.3 A as measured with a scan size of about 10 μm × about 10 μm;

thermally annealing the rough polished wafer at a temperature of at least about 1050° C. for a period of at least about 5 minutes in an atmosphere comprising an inert gas, hydrogen or a mixture thereof, wherein the wafer is not finish polished after the rough polishing step.

22. The method as set forth in claim 21 wherein the atmosphere in which the polished wafer is thermally annealed comprises an inert gas.

23. The method as set forth in claim 22 wherein the inert gas is argon.

24. The method as set forth in claim 21 wherein the atmosphere in which the polished wafer is thermally annealed consists essentially of an inert gas.

25. The method as set forth in claim 24 wherein the inert gas is argon.

26. The method as set forth in claim 21 wherein the thermal anneal reduces the roughness of the front surface of the wafer to below about 2.5 Å as measured with a scan size of about 100 μm × about 100 μm.

27. A method for reducing the surface roughness of a semiconductor wafer having a front surface and a back surface, the method comprising:

rough polishing the front surface and back surface of the wafer, wherein the polishing step does not reduce the roughness of the front surface and back surface of the wafer to below about 1.5 A as measured with scan sizes of about 1 μm × about 1 μm to about 100 μm × about 100 μm; and

thermally annealing the polished wafer, wherein the thermal anneal reduces the surface roughness of the front surface and back surface of the wafer to below about 1.5 A as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30μm, wherein the wafer is not finish polished after the rough polishing step.

28. The method of claim 27 wherein the thermal anneal reduces the roughness of the front surface of the wafer to between about 0.6 Å and about 1.5 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

29. The method of claim 26 wherein the wafer is thermally annealed at a temperature of from about 1050° C. to about 1350° C. in an atmosphere comprising an inert gas, hydrogen or a mixture thereof.

30. The method of claim 28 wherein the wafer is thermally annealed at a temperature of at least about 1050° C. for a period of at least about 5 minutes.

31. The method of claim 28 wherein the wafer is thermally annealed at a temperature of at least about 1050° C. for a period of at least about 10 minutes.

32. The method of claim 28 wherein the wafer is thermally annealed at a temperature of at least about 1150° C. for a period of at least about 10 minutes so as to create a substantially void-free region at least about 10 μm in thickness at the front surface of the wafer.

33. The method of claim 28 wherein the wafer is thermally annealed at a temperature of at least about 1200° C. for a period of at least about 1 hour so as to create a substantially void-free region at least about 10 μm in thickness at the front surface of the wafer.

34. The method of claim 28 wherein the rough polishing step does not reduce the roughness of the front surface of the wafer to below about 1.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 100 μm × about 100 μm.

35. The method of claim 28 wherein the rough polishing step removes a surface thickness on the front surface of the wafer of between about 1 μm and about 20 μm.

36. The method of claim 28 wherein the thermal anneal reduces the roughness of the back surface of the wafer to below about 1.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

37. The method of claim 28 wherein the thermal anneal reduces localized light scatterers on the front surface of the wafer caused by scratches, roughness and surface defects and greater than about 45 nm in diameter to less than about 25.

38. The method of claim 27 wherein the wafer is thermally annealed at a temperature of from about 1050° C. to about 1350° C. in an atmosphere comprising an inert gas, hydrogen or a mixture thereof.

39. The method of claim 27 wherein the thermal anneal reduces the roughness of the front surface of the wafer to between about 0.7 Å and about 1.5 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

40. The method of claim 27 wherein the thermal anneal reduces the roughness of the front surface of the wafer to about 0.9 Å as measured with scan sizes of about 1 μm × about 1 μm to about 30 μm × about 30 μm.

41. The method as set forth in claim 22 wherein the atmosphere in which the polished wafer is thermally annealed comprises an inert gas.

42. The method as set forth in claim 41 wherein the inert gas is argon.

43. The method as set forth in claim 29 wherein the atmosphere in which the polished wafer is thermally annealed consists essentially of an inert gas.

44. The method as set forth in claim 43 wherein the inert gas is argon.

45. The method as set forth in claim 27 wherein the thermal anneal reduces the roughness of the front surface of the wafer to below about 2.5 Å as measured with a scan size of about 100 μm × about 100 μm.

46. A method for reducing the surface roughness of a semiconductor wafer having a front surface and a back surface, wherein the resulting wafer contains a substantially void-free region at least about i0˜m in thickness at the front surface of the wafer, the method comprising:

rough polishing the front surface and back surface of the wafer, wherein the polishing step does not reduce the roughness of the front surface and back surface of the wafer to below about 1.5 A as measured with scan sizes of about 1 μm × about 1 μm to about 100 μm × about 100 μm; and

thermally annealing the rough polished wafer at a temperature of at least about 1150° C. for a period of at least about 10 minutes in an atmosphere comprising an inert gas, hydrogen or a mixture thereof , wherein the wafer is not finish polished after the rough polishing step.

47. The method of claim 46 wherein the polished wafer is thermally annealed at a temperature of at least about 1200° C. for a period of at least about 1 hour in an atmosphere comprising an inert gas, hydrogen or a mixture thereof.

48. The method of claim 46 wherein the thermal anneal reduces localized light scatterers on the front surface of the wafer caused by scratches, roughness and surface defects and greater than about 45 nm in diameter to less than about 25.

49. The method as set forth in claim 46 wherein the atmosphere in which the polished wafer is thermally annealed comprises an inert gas.

50. The method as set forth in claim 49 wherein the inert gas is argon.

51. The method as set forth in claim 46 wherein the atmosphere in which the polished wafer is thermally annealed consists essentially of an inert gas.

52. The method as set forth in claim 51 wherein the inert gas is argon.

53. The method as set forth in claim 46 wherein the thermal anneal reduces the roughness of the front surface of the wafer to below about 2.5 Å as measured with a scan size of about 100 μm × about 100 μm.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
SECURITY AGREEMENT Recorded Apr 1, 2011
From: MEMC ELECTRONIC MATERIALS, INC.; SUNEDISON LLC; SOLAICX
To: BANK OF AMERICA, N.A.
Reel/Frame 026064/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2008
From: SHIVE, LARRY W.; GILMORE, BRIAN L.
To: MEMC ELECTRONIC MATERIALS, INC.
Reel/Frame 020574/0531 →