IP Library Granted Patent US 8,153,538
Granted Patent B1
US 8,153,538 · App. 12/964,143 · Granted Apr 10, 2012

Process for annealing semiconductor wafers with flat dopant depth profiles

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Quick Facts
Patent No.
US 8,153,538
App. No.
12/964,143
Granted
Apr 10, 2012
Kind
B1
Abstract

A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Claims (18)

1. A process for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of a radial width, the process comprising:

annealing the wafer in an annealing chamber having an atmosphere comprising oxygen; and

maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing, the oxide layer having a maximum thickness of about 5 nanometers and a minimum thickness of about 0.5 nanometers so that the annealed front surface is substantially free of boron and phosphorus.

2. The process of claim 1 wherein the atmosphere further comprises hydrogen and an inert gas.

3. The process of claim 2 wherein the atmosphere comprises at least about 0.5% hydrogen.

4. The process of claim 2 wherein the inert gas is argon.

5. The process of claim 1 wherein the atmosphere comprises from about 1 ppm to about 5 ppm of oxygen.

6. The process of claim 1 wherein the silicon wafer is annealed at a temperature between about 900° C. and about 1050° C.

7. The process of claim 1 wherein the silicon wafer is annealed at a temperature of about 1000° C.

8. The process of claim 1 wherein the silicon wafer is annealed for a time of at least about 10 minutes.

9. The process of claim 1 wherein the silicon wafer is annealed for a time of about 30 minutes.

10. The process of claim 1 further comprising a second anneal separate from a first-referenced anneal in an atmosphere consisting essentially of inert gas.

11. The process of claim 10 wherein the second anneal is performed at a temperature between about 1150° C. and 1250° C.

12. The process of claim 11 wherein the temperature is held at 1200° C. for 1 hour.

13. The process of claim 12 wherein the temperature is ramped down to 450° C.

14. The process of claim 1 wherein a gas flow rate in the annealing chamber is about 20 standard liters per minute.

15. The process of claim 1 wherein the wafer is a P-type wafer.

16. The process of claim 1 wherein the wafer is at least 400 mm in diameter.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →