IP Library Granted Patent US 8,080,464
Granted Patent B2
US 8,080,464 · App. 12/971,788 · Granted Dec 20, 2011

Methods for processing silicon on insulator wafers

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Quick Facts
Patent No.
US 8,080,464
App. No.
12/971,788
Granted
Dec 20, 2011
Kind
B2
Abstract

Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

Claims (29)

1. A method for processing a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising the steps of:

inserting the structure into a reactor;

etching the cleaved surface while controlling a temperature of the reactor such that the etching reaction is kinetically limited; and

depositing an epitaxial layer on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

2. The method of claim 1 wherein the temperature of the reactor during etching is between 900° C. and 950° C.

3. The method of claim 1 wherein the temperature of the reactor during depositing is set between 950° C. and 1050° C. when a deposition gas is trichlorosilane.

4. A method for processing a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising the steps of:

inserting the structure into a reactor;

setting a temperature of the reactor such that a rate of etching of the cleaved surface will be kinetically limited;

initiating a flow of gaseous etchant into the reactor; and

etching the cleaved surface.

5. The method of claim 4 wherein the etching step comprises removing at least some of the silicon layer of the structure.

6. The method of claim 4 wherein the gaseous etchant is a mix of hydrogen and hydrogen chloride.

7. The method of claim 4 wherein the temperature of the reactor is set between 900° C. and 950° C.

8. The method of claim 7 wherein the temperature of the reactor is set at 950° C.

9. The method of claim 7 wherein the temperature of the reactor is set at 925° C.

10. The method of claim 4 further comprising stopping the flow of gaseous etchant once a first amount of the silicon layer of the cleaved surface is removed by the gaseous etchant.

11. The method of claim 10 further comprising performing an epitaxial deposition process on the structure after the flow of gaseous etchant has been stopped.

12. A method of processing a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising the steps of:

inserting the structure into a reactor;

setting a temperature of the reactor such that a rate of deposition of silicon on the cleaved surface will be kinetically limited;

initiating a flow of deposition gas into the reactor; and

depositing silicon onto the cleaved surface of the structure.

13. The method of claim 12 wherein the deposition gas contains at least one of: monosilane, dichlorosilane, trichlorosilane, and tetrachlorosilane.

14. The method of claim 12 wherein the depositing step includes depositing silicon contained in the deposition gas onto the cleaved surface of the structure.

15. The method of claim 12 wherein the temperature of the reactor is set between 950° C. and 1050° C. when the deposition gas is trichlorosilane.

16. The method of claim 15 wherein the temperature of the reactor is set at 1000° C.

17. The method of claim 12 further comprising stopping the flow of deposition gas once a first thickness of silicon has been deposited onto the cleaved surface of the structure.

18. The method of claim 12 further comprising removing the structure from the reactor.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2011
From: DHUMAL, SWAPNIL Y.; FLANNERY, LAWRENCE P.; TORACK, THOMAS A.; PITNEY, JOHN A.
To: MEMC ELECTRONIC MATERIALS, INC.
Reel/Frame 025897/0977 →