IP Library Patent Application 15191975
Patent Application
App. No. 15/191,975

METHODS FOR PREPARING LAYERED SEMICONDUCTOR STRUCTURES AND RELATED BONDED STRUCTURES

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Patent No.
US None
App. No.
15/191,975
Abstract

Methods for preparing silicon-on-insulator structures and related intermediate structures are disclosed. In some embodiments, a single crystal silicon seed crystal is bonded to an amorphous silicon layer disposed on a substrate and the amorphous layer is crystallized to form a monocrystalline silicon layer.

Claims (32)

1 . A method for preparing a layered semiconductor structure having a monocrystalline silicon device layer, the method comprising:

depositing an amorphous silicon layer on a substrate, the amorphous silicon layer and substrate forming an amorphous layer-substrate interface;

bonding a single crystal silicon seed wafer on the amorphous silicon layer to form a bonded structure, the single crystal silicon seed wafer and amorphous silicon layer forming a seed-amorphous layer interface;

annealing the bonded structure to crystallize the amorphous silicon layer and generate a monocrystalline silicon device layer from the amorphous silicon layer; and

cleaving the bonded structure to separate the single crystal silicon seed wafer from the bonded structure and form a layered product structure comprising the substrate and the monocrystalline silicon device layer.

2 . The method as set forth in claim 1 wherein the amorphous silicon layer is crystallized from the seed-amorphous layer interface toward the amorphous layer-substrate interface.

3 . The method as set forth in claim 1 wherein the substrate is selected from the group consisting of a silicon wafer, quartz, sapphire, ceramics, glass, germanium, silicon germanium, gallium nitride and aluminum nitride.

4 . The method as set forth in claim 1 wherein the amorphous silicon layer has a bonding surface, the bonding surface having a surface roughness from about 0.1 nm to about 1.0 nm at a scan size of about 30 μm by about 30 μm prior to bonding the single crystal silicon seed wafer on the amorphous silicon layer to form the bonded structure.

5 . The method a set forth in claim 1 wherein the single crystal silicon seed wafer has a bonding surface, the bonding surface having a surface roughness from about 0.1 nm to about 0.2 nm at a scan size of about 30 μm by about 30 μm prior to bonding the single crystal silicon seed wafer on the amorphous silicon layer to form the bonded structure.

6 . The method as set forth in claim 1 wherein the amorphous silicon wafer has a bonding surface and the single crystal silicon seed wafer has a bonding surface, the method comprising activating the surfaces to render the surfaces hydrophobic prior to bonding the single crystal silicon seed wafer to the amorphous silicon layer to form the bonded structure.

7 . The method as set forth in claim 1 wherein the amorphous silicon layer is a first amorphous silicon layer, the substrate is a first substrate, the bonded structure is a first bonded structure and the layered product structure is a first layered product structure, the method comprising:

depositing a second amorphous silicon layer on a second substrate;

bonding the cleaved single crystal silicon seed wafer on the second amorphous silicon layer to form a second bonded structure, the second single crystal silicon seed wafer and second amorphous silicon layer forming a seed-amorphous layer interface;

annealing the second bonded structure to crystallize the amorphous silicon layer and generate a monocrystalline silicon layer from the second amorphous silicon layer; and

cleaving the second bonded structure to separate the single crystal silicon seed wafer from the bonded structure and form a second layered product structure comprising the second substrate and the monocrystalline silicon layer.

8 . The method as set forth claim 1 wherein the amorphous silicon layer is deposited by chemical vapor deposition.

9 . The method as set forth in claim 1 wherein the amorphous silicon layer and/or monocrystalline silicon layer have a thickness of from about 10 nm to about 10 μm.

10 . The method as set forth in claim 1 wherein the amorphous silicon layer and/or monocrystalline silicon layer have a thickness of from about 50 nm to about 150 nm.

11 . The method as set forth in claim 1 wherein the bonded structure is cooled after annealing, the bonded structure cleaving during cooling due to thermal stress within the bonded structure.

12 . The method as set forth in claim 1 wherein the amorphous silicon layer is a continuous layer.

13 . The method as set forth in claim 1 wherein the bonded structure is annealed at a temperature from about 500° C. to about 580° C. to crystallize the amorphous silicon layer and generate a monocrystalline silicon device layer from the amorphous silicon layer.

14 . A bonded structure comprising:

a substrate selected from the group consisting of a silicon wafer, quartz, sapphire, ceramics, glass, germanium, silicon germanium, gallium nitride and aluminum nitride.

a single crystal silicon seed wafer; and

an amorphous silicon layer disposed between the substrate and the single crystal silicon seed wafer, the amorphous silicon layer and substrate forming an amorphous layer-substrate interface, the single crystal silicon seed wafer and amorphous silicon layer forming a seed-amorphous layer interface.

15 . The bonded structure as set forth in claim 14 wherein the amorphous silicon layer has a thickness of from about 10 nm to about 10 μm.

16 . The bonded structure as set forth in claim 14 wherein the amorphous silicon layer has a thickness of from about 50 nm to about 150 nm.

17 . A bonded structure comprising:

a substrate selected from the group consisting of a silicon wafer, quartz, sapphire, ceramics, glass, germanium, silicon germanium, gallium nitride and aluminum nitride;

a single crystal silicon seed wafer; and

a monocrystalline silicon device layer disposed between the substrate and the single crystal silicon seed wafer, the monocrystalline silicon device layer and substrate forming a device layer-substrate interface, the single crystal silicon seed wafer and monocrystalline silicon device layer forming a seed-device layer interface.

18 . The bonded structure as set forth in claim 17 wherein the monocrystalline silicon device layer has a thickness of from about 10 nm to about 10 μm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2016
From: WANG, GANG; LIBBERT, JEFFREY L.; LIU, QINGMIN; USENKO, ALEX; THOMAS, SHAWN GEORGE
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 040254/0620 →