IP Library Granted Patent US 6,930,375
Granted Patent B2
US 6,930,375 · App. 10/177,444 · Granted Aug 16, 2005

Silicon on insulator structure having an epitaxial layer and intrinsic gettering

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Quick Facts
Patent No.
US 6,930,375
App. No.
10/177,444
Granted
Aug 16, 2005
Kind
B2
Abstract

The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Claims (40)

1. A silicon on insulator structure comprising a device layer, a supporting layer and a dielectric layer therebetween, wherein the device layer comprises an epitaxial layer and the supporting layer comprises

(i) a first region and a second region, the first region extending from the dielectric layer to the second region and having a thickness, T, as measured from the dielectric layer to the second region, and

(ii) a non-uniform concentration of crystal lattice vacancies, the concentration of the vacancies in the second region being greater than the concentration of vacancies in the first region.

2. The silicon on insulator structure of claim 1 wherein the supporting layer, upon being subjected to an oxygen precipitation heat treatment consisting essentially of annealing the silicon on insulator structure at 800° C. for four hours and then at 1000° C. for sixteen hours, contains oxygen precipitates having a concentration profile in which a peak density of the precipitates is in the second region at or near a central plane with the concentration of the precipitates in the second region generally decreasing in the direction of the first region.

3. The silicon on insulator structure of claim 1 wherein the first region has a thickness of at least about 5 microns.

4. The silicon on insulator structure of claim 1 wherein the first region has a thickness of at least about 10 microns.

5. The silicon on insulator structure of claim 1 wherein the first region has a thickness of at least about 20 microns.

6. The silicon on insulator structure of claim 1 wherein the first region has a thickness of at least about 50 microns.

7. The silicon on insulator structure of claim 1 wherein the epitaxial layer has a thickness within the range of at least about 0.1 μm to less than about 2 μm.

8. The silicon on insulator structure of claim 1 wherein the epitaxial layer has a thickness within the range of about 0.25 to about 1 μm.

9. The silicon on insulator structure of claim 1 wherein the supporting layer has a carbon concentration which is less than about 1×10 16 atoms/cm 3 .

10. A silicon on insulator structure comprising a device layer, a supporting layer and a dielectric layer therebetween, wherein the device layer comprises an epitaxial layer and the supporting layer comprises

(i) a first region and a second region, the first region extending from the dielectric layer to the second region and having a thickness, T, as measured from the dielectric layer to the second region, and

(ii) a non-uniform depth distribution of stabilized oxygen precipitates, the concentration of the precipitates in the second region being greater than the concentration of precipitate in the first region.

11. The silicon on insulator structure of claim 10 wherein the supporting layer has a stabilized oxygen precipitate concentration profile in which a peak density of the precipitates is in the second region at or near a central plane with the concentration of the precipitates in the second region generally decreasing in the direction of the first region.

12. The silicon on insulator structure of claim 10 wherein the first region has a thickness of at least about 5 microns.

13. The silicon on insulator structure of claim 10 wherein the first region has a thickness of at least about 10 microns.

14. The silicon on insulator structure of claim 10 wherein the first region has a thickness of at least about 20 microns.

15. The silicon on insulator structure of claim 10 wherein the first region has a thickness of at least about 50 microns.

16. The silicon on insulator structure of claim 10 wherein the first region has a thickness ranging from about 5 microns to less than about 100 microns.

17. The silicon on insulator structure of claim 10 wherein the epitaxial layer has a thickness within the range of at least about 0.1 μm to less than about 2 μm.

18. The silicon on insulator structure of claim 10 wherein the epitaxial layer has a thickness within the range of about 0.25 to about 1 μm.

19. The silicon on insulator structure of claim 10 wherein the supporting layer has a carbon concentration which is less than about 1×10 16 atoms/cm 3 .

20. The silicon on insulator structure of claim 10 wherein the oxygen precipitates have an average cross-sectional area of at least about 40 nm.

21. The silicon on insulator structure of claim 10 wherein the oxygen precipitates have an average cross-sectional area of at least about 50 nm.

22. The silicon on insulator structure of claim 10 wherein the oxygen precipitates have an average cross-sectional area of at least about 60 nm.

23. The silicon on insulator structure of claim 10 wherein the oxygen concentration of the supporting layer is at least about 6×10 17 atoms/cm 3 .

24. A silicon on insulator structure comprising a device layer, a supporting layer and a dielectric layer therebetween, wherein the device layer comprises an epitaxial layer and the supporting layer comprises

(i) a first region and a second region, the first region extending from the dielectric layer to the second region and having a thickness, T, as measured from the dielectric layer to the second region, and

(ii) a non-uniform depth distribution of secondary defects capable of acting as intrinsic gettering sites, the concentration of defects in the second region being greater than the concentration of defects in the first region.

25. The silicon on insulator structure of claim 24 wherein the supporting layer has a secondary defect concentration profile in which a peak density of the defects is in the second region at or near a central plane with the concentration of the defects in the second region generally decreasing in the direction of the first region.

26. The silicon on insulator structure of claim 24 wherein the first region has a thickness of at least about 5 microns.

27. The silicon on insulator structure of claim 24 wherein the first region has a thickness of at least about 10 microns.

28. The silicon on insulator structure of claim 24 wherein the first region has a thickness of at least about 20 microns.

29. The silicon on insulator structure of claim 24 wherein the first region has a thickness ranging from about 5 microns to less than about 100 microns.

30. The silicon on insulator structure of claim 24 wherein the epitaxial layer has a thickness within the range of at least about 0.1 μm to less than about 2 μm.

31. The silicon on insulator structure of claim 24 wherein the epitaxial layer has a thickness within the range of about 0.25 to about 1 μm.

32. The silicon on insulator structure of claim 24 wherein the supporting layer has a carbon concentration which is less than about 1×10 16 atoms/cm 3 .

33. The silicon on insulator structure of claim 24 wherein the oxygen concentration of the supporting layer is at least about 6×10 17 atoms/cm 3 .

34. The silicon on insulator structure of claim 24 wherein the secondary defects are prismatic dislocation loops or tangles, or stacking faults.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST TO REEL/FRAME: 013964/0378 Recorded Mar 17, 2014
From: CITICORP USA, INC.
To: MEMC ELECTRONIC MATERIALS, INC. (NOW KNOWN AS SUNEDISON, INC.); MEMC PASADENA, INC.; PLASMASIL, L.L.C.; SIBOND, L.L.C.; MEMC SOUTHWEST INC.; MEMC INTERNATIONAL, INC. (NOW KNOWN AS SUNEDISON INTERNATIONAL, INC.)
Reel/Frame 032458/0958 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
SECURITY AGREEMENT Recorded Apr 1, 2011
From: MEMC ELECTRONIC MATERIALS, INC.; SUNEDISON LLC; SOLAICX
To: BANK OF AMERICA, N.A.
Reel/Frame 026064/0720 →