Bulk silicon wafer product useful in the manufacture of three dimensional multigate MOSFETs
View Patent ↗A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination.
1. A semiconductor structure comprising:
(a) a silicon substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a central plane between and parallel to the front and back surfaces, a circumferential edge, and a radius extending from the central axis to the circumferential edge;
(b) an epitaxial layer having a front surface and a back surface, wherein the back surface of the epitaxial layer is contiguous with the front surface of the silicon substrate, the epitaxial layer comprising:
(1) a surface epitaxial region extending an average transverse distance, D 1 , as measured from the front surface of the epitaxial layer toward the central plane;
(2) an endpoint detection epitaxial region extending an average transverse distance, D 2 , as measured from the surface epitaxial region toward the central plane; and
(3) a bulk epitaxial region extending an average transverse distance, D 3 , as measured from the endpoint detection epitaxial region toward the central plane;
wherein the endpoint detection epitaxial region comprises an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination thereof present in the endpoint detection epitaxial region at a concentration from about 1×10 17 atoms/cm 3 (about 2 PPM) to about 5×10 19 atoms/cm 3 (about 1000 PPMA), the concentration being at least 100 times a concentration of the endpoint detection impurity in the surface epitaxial region.
2. The semiconductor structure of claim 1 wherein the concentration of the endpoint detection impurity in the endpoint detection epitaxial region is at least 1000 times the concentration of the endpoint detection impurity in the surface epitaxial region.
3. The semiconductor structure of claim 1 wherein the concentration of the endpoint detection impurity in the endpoint detection epitaxial region is at least 10,000 times the concentration of the endpoint detection impurity in the surface epitaxial region.
4. The semiconductor structure of claim 1 wherein D 1 is from about 50 nanometers to about 400nanometers.
5. The semiconductor structure of claim 4 wherein D 1 has a total thickness variation between about 0.5% and about 4%.
6. The semiconductor structure of claim 1 wherein the surface epitaxial region comprises a fin.
7. The semiconductor structure of claim 6 wherein the fin extends a height as measured from the front surface of the epitaxial layer toward the central plane from about 50 nanometers to about 400 nanometers.
8. The semiconductor structure of claim 1 wherein D 2 is from about 5 nm to about 100 nm.