Methods for preparing a semiconductor wafer with high thermal conductivity
View Patent ↗This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.
1. A process for the preparation of a semiconductor wafer comprising a substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge, wherein the substrate has a dopant concentration of above 1×10 15 carriers/cm 3 and below about 1×10 17 carriers/cm 3 , the process comprising:
forming a protective layer on the front surface of the substrate, the protective layer being doped with a dopant concentration between about 3.2×10 18 carriers/cm 3 and about 1.0×10 20 carriers/cm 3 and having a thickness of at least about 0.5 μm;
forming a device layer on the exposed surface of the protective layer parallel to the front surface of the substrate, the device layer being doped with a P-type dopant at a dopant concentration greater than 1×10 14 carriers/cm 3 and below about 1×10 17 carriers/cm 3 ; and
exposing the back surface of the substrate to an alkaline etchant for a time period sufficient to remove substantially all of the substrate, thereby exposing the protective layer.
2. The process of claim 1 wherein the protective layer is formed by exposing the surface of the substrate to an atmosphere comprising silicon and a dopant to deposit a silicon epitaxial layer.
3. The process of claim 1 wherein the protective layer is formed by implanting dopant ions in the surface of the substrate.
4. The process of claim 1 wherein the protective layer is formed by exposing the surface of the substrate to a gas comprising a dopant to form a gas phase-doped layer.
5. The process of claim 1 wherein the protective layer has a thickness between about 2 μm and about 5 μm.
6. The process of claim 1 wherein the protective layer is doped with a dopant concentration between about 8.5×10 18 carriers/cm 3 and about 2.0×10 19 carriers/cm 3 .
7. The process of claim 6 wherein the substrate has a dopant concentration between 1×10 15 carriers/cm 3 and about 1×10 16 carriers/cm 3 .
8. The process of claim 1 wherein the protective layer is doped with a dopant concentration between about 3.2×10 18 carriers/cm 3 and about 8.5×10 18 carriers/cm 3 .
9. The process of claim 1 wherein the device layer is doped with boron.
10. The process of claim 1 wherein:
the substrate is doped with a P-type dopant in a concentration between about 5×10 14 carriers/cm 3 and about 1×10 16 carriers/cm 3 ;
the protective layer is doped with a P-type dopant in a concentration between about 3.2×10 18 carriers/cm 3 and about 2.0×10 19 carriers/cm 3 , and has a thickness between about 1 μm and about 10 μm; and
the device layer is doped with a P-type dopant in a concentration between about 1×10 14 carriers/cm 3 and about 4×10 16 carriers/cm 3 .
11. A process for the preparation of a semiconductor wafer comprising a substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge, wherein the substrate has a dopant concentration below about 1×10 17 carriers/cm 3 , the process comprising:
forming a protective layer on the front surface of the substrate, the protective layer being doped with a dopant concentration between about 6.0×10 17 carriers/cm 3 and about 1.0×10 20 carriers/cm 3 and having a thickness of at least about 0.5 μm;
forming a device layer on the exposed surface of the protective layer parallel to the front surface of the substrate, the device layer being doped with a P-type dopant at a dopant concentration greater than 1×10 14 carriers/cm 3 and below about 1×10 17 carriers/cm 3 ; and
exposing the back surface of the substrate to an alkaline etchant for a time period sufficient to remove substantially all of the substrate, thereby exposing the protective layer.
12. A process for the preparation of a semiconductor wafer comprising a substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge, wherein the substrate is doped with a P-type dopant and has a dopant concentration below about 1×10 17 carriers/cm 3 , the process comprising:
forming a protective layer on the front surface of the substrate, the protective layer being doped with a P-type dopant at a dopant concentration between about 6.0×10 17 carriers/cm 3 and about 1.0×10 20 carriers/cm 3 and having a thickness of at least about 0.5 μm;
forming a device layer on the exposed surface of the protective layer parallel to the front surface of the substrate, the device layer being doped with a P-type dopant at a dopant concentration below about 1×10 17 carriers/cm 3 ; and
exposing the back surface of the substrate to an alkaline etchant for a time period sufficient to remove substantially all of the substrate, thereby exposing the protective layer.
13. A process for the preparation of a semiconductor wafer comprising a substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge, wherein the substrate is doped with an N-type dopant and has a dopant concentration below about 1×10 17 carriers/cm 3 , the process comprising:
forming a protective layer on the front surface of the substrate, the protective layer being doped with an N-type dopant at a dopant concentration between about 6.0×10 17 carriers/cm 3 and about 1.0×10 20 carriers/cm 3 and having a thickness of at least about 0.5 μm;
forming a device layer on the exposed surface of the protective layer parallel to the front surface of the substrate, the device layer being doped with an N-type dopant at a dopant concentration below about 1×10 17 carriers/cm 3 ; and
exposing the back surface of the substrate to an alkaline etchant for a time period sufficient to remove substantially all of the substrate, thereby exposing the protective layer.