IP Library Granted Patent US 8,846,493
Granted Patent B2
US 8,846,493 · App. 13/419,139 · Granted Sep 30, 2014

Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer

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Quick Facts
Patent No.
US 8,846,493
App. No.
13/419,139
Granted
Sep 30, 2014
Kind
B2
Abstract

Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.

Claims (51)

1. A method for preparing a silicon-on-insulator structure comprising a handle wafer, a silicon device layer, a dielectric layer between the handle wafer and the silicon device layer, the handle wafer having an axis, a radius, a front surface, a back surface, and a peripheral edge extending in the axial direction from the front surface to the back surface, wherein the front surface of the handle wafer forms an interface with the dielectric layer, with the handle-dielectric interface and back surface being perpendicular to the axis, and wherein the handle wafer further comprises a surface layer extending in the axial direction from the handle-dielectric interface towards the back surface to a depth, D sl which comprises a high resistivity region and a bulk layer extending from the surface layer towards the back surface, the handle wafer having a resistivity profile in which a peak resistivity R peak exists in the high-resistivity region, the resistivity generally decreasing from the peak resistivity towards the bulk layer, the method comprising:

selecting a handle wafer with a given dopant concentration and interstitial oxygen concentration, the handle wafer being doped with a dopant of a first type, the dopant of the first type being either a p-type or n-type dopant;

forming a high resistivity region in the surface layer of the handle wafer by

diffusing oxygen either into or out of the handle wafer to form a non-uniform distribution of oxygen in the handle wafer and annealing the wafer having a non-uniform distribution of oxygen to form a non-uniform distribution of thermal donors;

forming a dielectric layer on at least one surface of the donor wafer and/or the front surface of the handle wafer;

bonding a donor wafer and the handle wafer to form a bonded wafer wherein the donor wafer and handle wafer are separated along the axis by the dielectric layer, the dielectric layer forming a donor-dielectric interface between the donor wafer and dielectric layer and a handle-dielectric interface between the dielectric layer and front surface of the handle wafer, the bonded wafer comprising a bond interface located at the donor-dielectric interface, the handle-dielectric interface or in the dielectric layer between the two interfaces; and

removing a portion of the donor wafer from the bonded wafer such that a silicon layer remains bonded to the dielectric layer to form the silicon on insulator structure.

2. The method as set forth in claim 1 wherein the peak resistivity R peak generally decreases from the peak resistivity to the handle-dielectric interface.

3. The method as set forth in claim 1 wherein the handle wafer has a bulk resistivity of at least 50 ohm-cm prior to formation of the high resistivity region.

4. The method as set forth in claim 1 wherein the annealing step to form thermal donors is part of a silicon-on-insulator manufacturing process or electronic device manufacturing process.

5. The method as set forth in claim 1 wherein a high resistivity region in the handle wafer is created by a method consisting essentially of:

diffusing oxygen into the handle wafer through its front surface; and

performing a thermal donor generating anneal in which oxygen agglomerates and forms thermal donors.

6. The method as set forth in claim 1 wherein a high resistivity region in the handle wafer is created by a method consisting essentially of:

diffusing oxygen into the handle wafer through its front surface;

doping the handle wafer with a dopant of a second type through its front surface, the dopant of the second type being either a p-type or n-type dopant and being of a type different than the first type; and

performing a thermal donor generating anneal in which oxygen agglomerates and forms thermal donors.

7. The method as set forth in claim 1 wherein a high resistivity region in the handle wafer is created by a method consisting essentially of:

diffusing oxygen out of the handle wafer through its front surface;

performing a thermal donor generating anneal in which oxygen agglomerates and forms thermal donors.

8. The method as set forth in claim 1 wherein a high resistivity region in the handle wafer is created by a method consisting essentially of:

diffusing oxygen out of the handle wafer through its front surface;

doping the handle wafer with a dopant of a second type through its front surface, the dopant of the second type being either a p-type or n-type dopant and being of a type different than the first type; and

performing a thermal donor generating anneal in which oxygen agglomerates and forms thermal donors.

9. The method as set forth in claim 1 wherein oxygen is diffused either into or out of the handle wafer through its front surface to form a non-uniform distribution of oxygen in the handle wafer and the wafer having a non-uniform distribution of oxygen is annealed to form thermal donors, the thermal donor generating anneal being part of the SOI manufacturing process.

10. The method as set forth in claim 1 wherein oxygen is diffused either into or out of the handle wafer through its front surface to form a non-uniform distribution of oxygen in the handle wafer and the wafer having a non-uniform distribution of oxygen is annealed to form thermal donors, the thermal donor generating anneal being part a radio-frequency device manufacturing process.

11. The method as set forth in claim 1 wherein the peak resistivity R peak occurs at least 0.1 μm from the handle-dielectric interface.

12. The method as set forth in claim 1 wherein the peak resistivity R peak occurs at least 1 μm from the handle-dielectric interface.

13. The method as set forth in claim 1 wherein the peak resistivity R peak occurs at least 2 μm from the handle-dielectric interface.

14. The method as set forth in claim 1 wherein R peak occurs less than about 15 μm from the handle-dielectric interface.

15. The method as set forth in claim 1 wherein R peak is at least about 1000 ohm-cm.

16. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the ratio of R peak to R bulk is at least about 2:1.

17. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the ratio of R peak to R bulk is at least about 5:1.

18. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the difference in resistivity from the R peak and the R bulk is at least about 1,000 ohm-cm.

19. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the difference in resistivity from the R peak and the R bulk is at least about 2,000 ohm-cm.

20. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the difference in resistivity from the R peak and the R bulk is at least about 5,000 ohm-cm.

21. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the difference in resistivity from the R peak and the R bulk is at least about 7,500 ohm-cm.

22. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk and the difference in resistivity from the R peak and the R bulk is at least about 10,000 ohm-cm.

23. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the ratio of R peak to R HD is at least about 2:1.

24. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the ratio of R peak to R HD is at least about 5:1.

25. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the difference in resistivity from the R peak and the R HD is at least about 1,000 ohm-cm.

26. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the difference in resistivity from the R peak and the R HD is at least about 2,000 ohm-cm.

27. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the difference in resistivity from the R peak and the R HD is at least about 5,000 ohm-cm.

28. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the difference in resistivity from the R peak and the R HD is at least about 7,500 ohm-cm.

29. The method as set forth in claim 1 wherein the handle wafer has a resistivity R HD at the handle-dielectric interface and the difference in resistivity from the R peak and the R HD is at least about 10,000 ohm-cm.

30. The method as set forth in claim 1 wherein the bulk layer has an average resistivity R bulk , the high-resistivity region having a resistivity throughout the high resistivity region that exceeds the resistivity of the bulk R bulk by at least about 50%, the high resistivity region having a thickness D res , measured in the axial direction, of at least about 1 μm.

31. The method as set forth in claim 30 wherein the thickness D res of the high resistivity region is at least about 5 μm.

32. The method as set forth in claim 30 wherein the thickness D res of the high resistivity region is at least about 10 μm.

33. The method as set forth in claim 30 wherein the thickness D res of the high resistivity region is at least about 15 μm.

34. The method as set forth in claim 30 wherein the thickness D res of the high resistivity region is at least about 25 μm.

35. A method for preparing a radio-frequency device, the method comprising forming a SOI structure according to the method of claim 1 and subjecting the SOI structure to further processing to form a radio-frequency device on the SOI structure.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2012
From: LIBBERT, JEFFREY L.; FEI, LU; STANDLEY, ROBERT W.
To: MEMC ELECTRONIC MATERIALS, INC.
Reel/Frame 028141/0411 →