Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
View Patent ↗Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.
1. A method of reducing the metal content of a silicon on insulator structure comprising:
forming a sacrificial oxide layer on a front surface of a silicon device layer of a silicon on insulator structure, the silicon on insulator structure comprising a handle wafer, the silicon device layer and a dielectric layer between the handle wafer and the silicon layer, the dielectric layer and silicon device layer forming an interface between the dielectric layer and silicon device layer, the sacrificial oxide layer and the silicon device layer forming an interface between the sacrificial oxide layer and the silicon device layer;
heating the silicon on insulator structure having a sacrificial oxide layer thereon to a temperature T 1 sufficient to dissolve all metal precipitates present in the device layer for a time t 1 sufficient to allow metal atoms to evenly disperse throughout the device layer, wherein the dissolved metal atoms have a chemical potential at the sacrificial oxide layer-silicon device layer interface lower than the chemical potential for the atoms within the bulk of the device layer such that the atoms become pinned at the sacrificial oxide layer-silicon device layer interface and the silicon device layer-dielectric layer interface;
cooling the silicon on insulator structure from T 1 to a temperature T 2 at which the metal atoms are substantially immobile in silicon at an average cooling rate R the cooling rate being sufficiently high enough to cause substantially no metal precipitation to occur in the silicon device layer during cooling, the metal atoms migrating to their lowest chemical potential at the sacrificial oxide layer-silicon device layer interface and the silicon device layer-dielectric layer interface; and
removing the sacrificial oxide layer and a portion of the metal atoms at the sacrificial oxide layer-silicon device layer interface from the silicon-in-insulator structure.
2. The method as set forth in claim 1 wherein the silicon on insulator structure is heated for a time sufficient to allow the average lateral diffusion distance of the metal atoms to exceed the thickness of the device layer.
3. The method as set forth in claim 2 wherein the silicon on insulator structure is heated for a time sufficient to allow the lateral diffusion distance of the metal atoms to exceed the thickness of the device layer by about 100 times or more.
4. The method as set forth in claim 2 wherein the silicon on insulator structure is heated for a time sufficient to allow the lateral diffusion distance of the metal atoms to exceed the thickness of the device layer by about 1000 times or more.
5. The method as set forth in claim 1 wherein the temperature at the sacrificial oxide layer-silicon device layer interface exceeds the temperature at the silicon device layer-dielectric layer interface during cooling such that more metal atoms are positioned at the sacrificial oxide layer-silicon device layer interface than the silicon device layer-dielectric layer interface.
6. The method as set forth in claim 1 wherein the metal is selected from the group consisting of nickel, copper and cobalt.
7. The method as set forth in claim 1 wherein the metal is nickel.
8. The method as set forth in claim 7 wherein T 1 is about 490° C. or more.
9. The method as set forth in claim 1 wherein T 1 is at least the temperature at which the metal dissolves in the device layer and is no more than about 25° C. greater than the temperature at which the metal completely dissolves in the device layer.
10. The method as set forth in claim 7 wherein the time t 1 at which the silicon on insulator structure is heated is about 1 minute or more.
11. The method as set forth in claim 7 wherein the cooling rate R is about 0.3° C./min or more.
12. The method as set forth in claim 7 wherein T 2 is about 440° C.
13. The method as set forth in claim 7 wherein T 2 is about 440° C. or less.
14. The method as set forth in claim 1 wherein the sacrificial oxide layer is formed by exposing the structure to ambient air to form a native oxide layer.
15. The method as set forth in claim 1 wherein the sacrificial oxide layer is formed by heating the wafer in an oxygen-containing atmosphere.
16. The method as set forth in claim 1 wherein the silicon device layer is less than about 200 nm thick.
17. The method as set forth in claim 1 wherein the silicon device layer is less than about 75 nm thick.
18. The method as set forth in claim 1 wherein the initial concentration of nickel in the silicon on insulator structure is about 1×10 10 atoms/cm 3 or more.
19. The method as set forth in claim 1 wherein the initial concentration of nickel in the silicon device layer is about 1×10 10 atoms/cm 3 or more.
20. The method as set forth in claim 1 wherein the sacrificial oxide layer forming step, heating step, cooling step and sacrificial oxide layer removal step are repeated for about 2 cycles or more to further reduce the amount of metal in the silicon device layer.
21. The method as set forth in claim 1 wherein the dielectric layer is composed of SiO 2 .
22. The method as set forth in claim 1 wherein the silicon device layer comprises metal of a first type in an amount at or below the solubility limit of the metal in silicon at temperature T 1 after the sacrificial oxide layer is removed.
23. The method as set forth in claim 1 wherein the sacrificial oxide layer and a portion of the metal atoms at the sacrificial oxide layer-silicon device layer interface are removed by contacting the silicon on insulator structure with the sacrificial layer thereon is contacted with an etching solution.